La conversion analogique-numérique sigma-delta passe-bande à temps continu constitue une approche intéressante pour la numérisation directe de signaux radiofréquences. Pour faire un premier pas vers des systèmes de conversion rapides et agiles basés sur cette approche, la faisabilité d'un convertisseur sigma-delta passe-bande à fréquence centrale ajustable sur une bande de fréquence limitée est étudiée au travers de la conception d'un circuit intégré prototype en technologie GaAs P-HEMT 0.2 µm.<br />L'architecture du modulateur sigma-delta comprend un filtre de boucle à structure parallèle, afin d'assurer à la fois la stabilité et la précision du dispositif, un sommateur et un comparateur. Les filtres passe-bande, constitutifs du filtre de boucle, sont du type Gm-LC à résistance négative. Le retard optimal théorique pour cette architecture est de 1,25 Te (Te : période d'échantillonnage) et ce retard est approximativement atteint grâce à un comparateur verrouillable (1,12 Te). Le réglage de la fréquence centrale s'opère par le biais de varicaps dans le résonateur d'entrée. La simulation du circuit au niveau transistor permet d'évaluer une résolution de 10 bits sur une bande de 4 MHz pour une fréquence centrale de 750 MHz et une fréquence de sur-échantillonnage de 3 GHz. La fréquence centrale du modulateur peut être abaissée à 725 MHz où la résolution atteint 9 bits. La consommation est estimée à 5,7 W. Le circuit a été implanté et la surface de la puce s'élève à 12 mm2.<br />Ce travail présente une méthodologie de conception basée sur des simulations multi-niveaux (transistor, fonctionnel). Cette approche permet d'isoler l'impact des non-idéalités de chacun des blocs au niveau circuit sur le fonctionnement général du modulateur. Des solutions sont proposées pour la correction de ces défauts. La robustesse du circuit a aussi fait l'objet d'une étude en termes de dispersions technologiques et d'éléments parasites introduits par l'implantation. Des remèdes sont proposés pour pallier ces problèmes.

Dans ce travail intitulé « Conception de modulateurs Sigma-Delta d'ordre élevé pour convertisseurs analogique-numérique en parallèle », les travaux ont été menés dans le contexte de la radio logicielle. La voie proposée pour la réalisation du convertisseur analogique-numérique, élément clé et bloquant de la radio logicielle, est une structure composée de plusieurs modulateurs sigma-delta passe-bande à temps continu mis en parallèle. Après avoir énuméré les différentes spécifications auxquelles le modulateur doit satisfaire, une nouvelle méthodologie de design à été proposé. Un état de l'art des différentes technologies de réalisation des filtres du modulateur a été réalisé, aboutissant à l'utilisation de résonateurs à filtres à ondes d'onde de Lamb. Les caractéristiques de ce résonateur ont été présentées ainsi qu'un circuit de commande permettant la compensation des inconvénients. Après avoir défini une novelle topologie et le résonateur, une méthode pour optimiser les performances de chaque modulateur en fonction des imperfections de l'électronique utilisée pour l'implémentation en fonction de la fréquence centrale de chacun d'entre eux a été proposé. Un travail d'analyse permettant de mettre en évidence l'influence de chacun des défauts électroniques importants sur les performances globales du modulateur, que ce soit en termes de résolution ou de stabilité, a été développé. Le comportement de la fonction de transfert de signal (STF) du système optimisé ne correspond pas à un filtre sélecteur de bande. Une modification originale de la topologie du modulateur permettant l'amélioration de la réponse en fréquence de la STF sans modifier la fonction de transfert du bruit (NTF) a été proposée. Enfin, la réalisation d'un modulateur sigma-delta à temps continu du deuxième ordre au niveau layout a été effectuée. La réduction de l'ordre est justifiée par le fait que l'intégration d'un filtre à onde de Lamb n'est pas encore un processus bien maitrisé et que son utilisation dans un sixième ordre pourrait aboutir à un circuit inexploitable en termes d'analyse.

<p>The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost.</p><p>The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.</p>

State-of-the art electronic systems include ever more features and gather mixed-signal subsystems, possibly from different physical domains. At the same time, cost and development time are reduced; stressing the need for an efficient design flow for fast and reliable design. The present thesis contributes to the construction of an improved design flow supported by mixed-signal hardware description languages (HDL-AMS). In a hierarchical view, the electronic systems are recursively divided into subsystems, down to basic cells and transistor level. The typical design flow results of a top-down synthesis, from the system specifications to the physical realizations, and of a bottom-up validation, from the test of the basic cells up to the test of the system. To improve the link between the technological level and the basic cells, we develop a measurement-based analog ID card which aims to optimize the analog performance and the reliability at high temperature by enabling the choice of optimal process (bulk vs. partially-depleted silicon-on-insulator (SOI) vs. fully-depleted SOI), optimal devices (e.g. multi-threshold voltages process) and optimal bias (weak vs. moderate vs. strong inversion). In the present thesis, we deal with the following analog performance parameters: gain, gain-bandwidth product, MOSFET mismatch in weak inversion and harmonic distortion of MOSFETs in triode regime. We show that SOI transistors are still advantageous over bulk in deep-submicron CMOS technologies and that short-channel SOI transistors can safely be used for mixed-signal operation up to 250°C. The analog ID card can be included in the design flow supported by HDL-AMS. Behavioral models for the basic cells are developed using such languages and further assembled into a ÄÓ modulator with continuous-time integrators as it is a good candidate for low-power consumption and operation at high temperature. The related design issues are assessed using the behavioral models and a design optimization method is presented for a key building block, an active RC integrator with passive resistors.

Denna avhandling presenterar en undersökning av orsakerna och effekterna av timingosäkerhet i Sigma-Delta Analog-Digital-Omvandlare, med speciellt fokus på Sigma-Delta av den switchade kapacitanstypen. Det undersökta området för orsakerna till timingosäkerhet är digital klockgenerering och området för effekterna är sampling. Upplösningsnivån på analysen i detta arbete börjar på beteendenivå och slutar på transistornivå. Samplingskretsen är den intuitiva komponenten att söka i efter orsakerna till effekterna av timing-osäkerhet i en Analog-Digital-Omvandlare eftersom transformationen från reell tid till digital tid sker i samplingskretsen. Därför har prestandaeffekterna av timingosäkerhet i den typiska samplingskretsen för switchad kapacitans Sigma-Delta Analog-Digital-Omvandlare analyserats utförligt, modellerats och beskrivits i denna avhandling. Under analysprocessen har idéer om förbättrade samplingskretsar med naturlig tolerans mot timing-osäkerhet utvecklats och analyserats, och presenteras även. Två typer av förbättrade samplingstopologier presenteras: parallelsamplern och Sigma-Delta-samplern. Den första erhåller tolerans mot timing-osäkerhet genom att utnyttja ett teorem inom statistiken medan den andra är tolerant mot timing-osäkerhet p.g.a. spektral formning som trycker ut brus ur signalens frekvensband. Digital klockgenerering är ett fundamentalt steg i genereringen av multipla klocksignaler som behövs t.ex. i switchade kapacitansversioner av Sigma-Delta Analog-Digital-Omvandlare. Klockgeneratorkretsarna konverterar en tidsreferens, d.v.s. en klocksignal, som vanligen kommer från en faslåst loop till multipla tidsreferenser. De två typerna av klockgenereringskretsar som behandlas i denna avhandling används för att skapa två icke-överlappande klockor från en klocksignal. Processen som undersökts och beskrivits är hur matningsspänningsbrus och substratbrus omvandlas till timing-osäkerhet då en referenssignal passerar genom en av ovannämnda klockgenereringskretsar. Resultaten i denna avhandling har erhållits genom olika analystekniker. Modelleringarna och beskrivningarna har utförts från ett matematiskt och fysikaliskt perspektiv. Detta har fördelen av att kunna förutsäga prestandainfluenser som olika kretsparametrar har utan att behöva utföra datorsimuleringar. Svårigheterna med den matematiska och fysikaliska modelleringen är balansgången mellan olöslighet och överförenkling som måste hittas. Den andra infallsvinkeln är användandet av datorbaserade simuleringsverktyg både för beskrivnings- och verifieringsändamål. Simuleringsverktygen som använts är MATLAB och Spectre/Cadence. Som nämnts har deras syfte varit både som modell- och beskrivningsverifiering och även som ett sätt att erhålla kvantitativa resultat. Generellt talat bryter simuleringsverktyg den mentala kopplingen mellan resultat och diverse kretsparametrar och det kan vara svårt att uppnå en solid prestandaförståelse. Dock är det ibland bättre att erhålla ett prestandamått utan full förståelse än inget mått alls. / This dissertation presents an investigation of the causes and effects of timing uncertainty in Sigma-Delta Analog-to-Digital Converters, with special focus on the switched-capacitor Sigma-Delta type. The investigated field for cause of timing uncertainty is digital clock generation and the field for effect is sampling. The granularity level of the analysis in this work begins at behavioral level and finishes at transistor level. The sampling circuit is the intuitive component to look for the causes to the effects of timing uncertainty in an Analog-to-Digital Converter since the transformation from real time to digital time takes place in the sampling circuit. Hence, the performance impact of timing uncertainties in a typical sampling circuit of a switched-capacitor Sigma-Delta Analog-to-Digital Converter has been thoroughly analysed, modelled, and described in this dissertation. During the analysis process, ideas of improved sampling circuits with inherent tolerance to timing uncertainties were conceived and analysed, and are also presented. Two cases of improved sampling topologies are presented: the Parallel Sampler and the Sigma- Delta sampler. The first obtains its timing uncertainty tolerance from taking advantage of a theorem in statistics whereas the second is tolerant against timing uncertainties because of spectral shaping that effectively pushes the in-band timing noise out of the signal band. Digital clock generation is a fundamental step of generating multiple clock signals that are needed for example in switched-capacitor versions of Sigma-Delta Analog-to-Digital Converters. The clock generation circuitry converts a single time reference, i.e. a clock signal, usually coming from a phase-locked loop into multiple time references. The two types of clock-generation circuits that are treated in this dissertation are used to create two nonoverlapping clocks from a single clock signal. The process that has been investigated and described is how power-supply noise and substrate noise transforms into timing uncertainty when a reference signal is passed through one of the aforementioned clock generation circuits. The results presented in this dissertation have been obtained using different analysis techniques. The modelling and descriptions have been done from a mathematical and physical perspective. This has the benefit of predicting the performance impact by different circuit parameters without the need for computer based simulations. The difficulty with the mathematical and physical modelling is the balance that has to be found between intractability and oversimplification. The other angle of approach has been the use of computer based simulations for both description and verification purposes. The simulation tools that have been used in this work are MATLAB and Spectre/Cadence. As mentioned, their purpose has been both for model and description verification and also as a means of obtaining result metrics. Generally speaking, simulation tools mentally decouple the result from the various circuit parameters and reaching a solid performance understanding can be difficult. However, obtaining a performance metric without full comprehension can at times be better than having no metric at all. / QC 20100921

The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost. The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.

In low power, battery-operated, portable applications, like cell phones, PDAs, digital cameras, etc., miniaturization at a low cost is a prominent driving factor behind product development and marketing efforts. As such, power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because, in catering to all combinations of the output capacitor, its equivalent series resistance Resr, and the power inductor resulting from tolerance and modal design targets, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios. Sigma-delta control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide LC-Resr compliance in boost (step-up) converters. This thesis investigates and presents techniques to achieve sigma-delta control in boost converters by essentially using explicit current and voltage control loops. The proposed techniques are developed conceptually and analytical expressions for stability range and transient response are derived. The proposed concepts are validated and quantified through PCB and IC prototypes to yield 1.41 to 6 times faster transient response than the state of the art in current-mode boost supplies, and this without any compromise in LC-Resr compliance range.

This thesis presents the development of high resolution, wide dynamic range sigma-delta type readout circuits for capacitive MEMS accelerometers. Designed readout circuit employs fully differential closed loop structure with digital output, achieving high oversampling ratio and high resolution. The simulations of the readout circuit together with the accelerometer sensor are performed using the models constructed in Cadence and Matlab Simulink environments. The simulations verified the stability and proper operation of the accelerometer system. The sigma-delta readout circuit is implemented using XFab 0.6 &micro / m CMOS process. Readout circuit is combined with Silicon-On-Glass (SOG) and Dissolved Wafer Process (DWP) accelerometers. Both open loop and closed loop tests of the accelerometer system are performed. Open loop test results showed high sensitivity up to 8.1 V/g and low noise level of 4.8 &micro / g/&amp / #61654 / Hz. Closed loop circuit is implemented on a PCB together with the external filtering and decimation electronics, providing 16-bit digital output at 800 Hz sampling rate. High acceleration tests showed &plusmn / 18.5 g of linear acceleration range with high linearity, using DWP accelerometers. The noise tests in closed loop mode are performed using Allan variance technique, by acquiring the digital data. Allan variance tests provided 86 &micro / g/&amp / #61654 / Hz of noise level and 74 &micro / g of bias drift. Temperature sensitivity tests of the readout circuit in closed loop mode is also performed, which resulted in 44 mg/&ordm / C of temperature dependency. Two different types of new adaptive sigma-delta readout circuits are designed in order to improve the resolution of the systems by higher frequency operation. The two circuits both change the acceleration range of operation of the system, according to the level of acceleration. One of the adaptive circuits uses variation of feedback time, while the other circuit uses multi-bit feedback method. The simulation results showed micro-g level noise in closed loop mode without the addition of the mechanical noise of the sensor.

Micromachining technologies enabled the use of miniaturized transducers in many high technology sensing systems. These transducers have many advantages like small-size, low-cost and high-reliability. One of the applications micro-machined transducers are used is inertial navigation systems, where the exact position of a moving frame is continuously monitored by tracking the linear and angular motions of the frame. Other than navigation applications, inertial sensors are used in health and military applications as well as consumer electronics. Today accelerometers capable of measuring accelerations from 0.5g-1g range up to several thousand g&rsquo / s are commercially available in the market which have been fabricated using micromachining technologies. The aim of this research is to develop such a state-of-the-art micro-machined accelerometer system, whose performance is expected to reach tactical-grade level. In order to achieve these performance values a MATLAB algorithm is developed to optimize the accelerometer performances in the desired levels. Expected performance parameters of the designed accelerometer structures are extracted from the simulations done by both Coventorware finite element modeling tool and MATLAB. Designed structures are then fabricated with silicon-on-glass, dissolved wafer and dissolved epitaxial wafer processes. These fabrication results are compared and it is observed that highest yield accelerometers are fabricated with the SOG process. But these accelerometers could not be able to satisfy tactical grade performance parameters. Best performances are obtained with DWP, but due to high internal stress, yield of the sensors were very low. DEWP increased the yield of this process from 2-3% to 45-50% but the expected operation range of the designs dropped to &plusmn / 12.5g range. Using the fabricated accelerometers in DEWP a three axial accelerometer package is prepared and tests results proved that this three axial accelerometer system was satisfying the tactical grade requirements. In addition to these a three axial monolithic accelerometer fabrication technique is proposed and sensors are designed which are suitable for this process. Best performances achieved with single axis accelerometers were 153&micro / g/&radic / Hz noise floor, 50&micro / g bias drift, 0.38% non-linearity and a maximum operation range of 33.5g which has the higher dynamic range among its counterparts in the literature. Performance results achieved with the three axes accelerometer were ~150&micro / g bias drift, &lt / 200&micro / g/&radic / Hz noise density, ~0.4% non-linearity with higher than &plusmn / 10g operation range.

MEMS accelerometers are quickly approaching navigation grade performance and navigation market for MEMS accelerometer systems are expected to grow in the recent years. Compared to conventional accelerometers, these micromachined sensors are smaller and more durable but are generally worse in terms of noise and dynamic range performance. Since MEMS accelerometers are already dominant in the tactical and consumer electronics market, as they are in all modern smart phones today, there is significant demand for MEMS accelerometers that can reach navigation grade performance without significantly altering the developed process technologies. This research aims to improve the performance of previously fabricated and well-known MEMS capacitive closed loop &Sigma / &Delta / accelerometer systems to navigation grade performance levels. This goal will be achieved by reducing accelerometer noise level through significant changes in the system architecture and implementation of a new electronic interface readout ASIC. A flexible fourth order &Sigma / &Delta / modulator was chosen as the implementation of the electro-mechanical closed loop system, and the burden of noise shaping in the modulator was shifted from the mechanical sensor to the programmable electronic readout. A novel operational transconductance amplifier (OTA) was also designed for circuit implementation of the electronic interface readout. Design and fabrication of the readout was done in a standard 0.35 &micro / m CMOS technology. With the newly designed and fabricated readout, single-axis accelerometers were implemented and tested for performance levels in 1g range. The implemented system achieves 5.95 &micro / g/sqrt Hz, 6.4 &micro / g bias drift, 131.7 dB dynamic range and up to 37.2 g full scale range with previously fabricated dissolved epitaxial wafer process (DEWP) accelerometers in METU MEMS facilities. Compared to a previous implementation with the same accelerometer element reporting 153 &micro / g/sqrtHz, 50 &micro / g bias drift, 106.8 dB dynamic range and 33.5 g full scale range / this research reports a 25 fold improvement in noise, 24 dB improvement in dynamic range and removal of the deadzone region.