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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
151

Mitigation of harmonic and inter-harmonic effects in nonlinear power converters

Cho, Won Jin 03 February 2011 (has links)
Harmonic distortions are inevitably caused by a rectifier and an inverter due to their inherent nonlinearities. An AC-DC-AC converter, configured by the series connection of a rectifier, DC link, and an inverter, induces harmonic distortions at both AC sides and at the DC link. These harmonics can nonlinearly interact or modulate the fundamental frequencies at the AC sides to cause interharmonic distortions. Harmonic and interharmonic distortions can seriously hamper the normal operation of the power system by means of side effects such as excitation of undesirable electrical and/or mechanical resonances, misoperation of control devices, and so forth. This dissertation presents effective methodologies to mitigate harmonic and interharmonic distortions by applying dithered pulse-width modulated (PWM) signals to a voltage-sourced inverter (VSI) type adjustable speed drive (ASD). The proposed methods are also efficient because the dithering applications are performed on control signals without the need for additional devices. By the help of dithering, the rejection bandwidth of a harmonic filter can be relaxed, which enables a lower-order configuration of harmonic filters. First, this dissertation provides a dithering application on gating signals of a sinusoidal PWM (SPWM) inverter in the simulated VSI-ASD model. The dithering is implemented by adding intentional noise into the SPWM process to randomize rising and falling edges of each pulse in a PWM waveform. As a result of the randomized edges, the periodicity of each pulse is varied, which result in mitigated harmonic tones. This mitigation of PWM harmonics also reduces associated interharmonic distortions at the source side of the ASD. The spectral densities at harmonic and interharmonic frequencies are quanti fied by Fourier analysis. It demonstrates approximately up to 10 dB mitigation of harmonic and interharmonic distortions. The nonlinear relationship between the mitigated interharmonics and harmonics is confirmed by cross bicoherence analysis of source- and DC-side current signals. Second, this dissertation proposes a dithered sigma-delta modulation (SDM) technique as an alternative to the PWM method. The dithering method spreads harmonic tones of the SD M bitstream into the noise level. The noise-shaping property of SDM induces lower noise density near the fundamental frequency. The SDM bitstream is then converted into SDM waveform after zero-order interpolation by which the noise-shaping property repeats at every sampling frequency of the bitstream. The advantages of SDM are assessed by comparing harmonic densities and the number of switching events with those of SPWMs. The dithered SD M waveform bounds harmonic and noise densities below approximately -30 dB with respect to the fundamental spectral density without increasing the number of switching events. Third, this dissertation provides additional validity of the proposed method via hardware experiments. For harmonic assessment, a commercial three-phase inverter module is supplied by a DC voltage source. Simulated PWM signals are converted into voltage waveforms to control the inverter. To evaluate interharmonic distortions, the experimental configuration is extended to a VSI-ASD model by connecting a three-phase rectifier to the inverter module via a DC link. The measured voltage and current waveforms are analyzed to demonstrate coincident properties with the simulation results in mitigating harmonics and interharmonics. The experimental results also provide the efficacy of the proposed methods; the dithered SPWM method effectively mitigates the fundamental frequency harmonics and associated interharmonics, and the dithered SDM reduces harmonics with the desired noise-shaping property. / text
152

Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA

Dubois, Matthieu 23 June 2011 (has links) (PDF)
L'expansion du marché des semi-conducteurs dans tous les secteurs d'activité résulte de la capacité de créer de nouvelles applications grâce à l'intégration de plus en plus de fonctionnalités sur une surface de plus en plus faible. Pour chaque entreprise, la compétitivité dépend du coût de fabrication mais aussi de la fiabilité du produit. Ainsi, la phase de test d'un circuit intégré, et plus particulièrement des circuits analogiques et mixtes, est le facteur prédominant dans les choix d'un compromis entre ces deux critères antagonistes, car son coût est désormais proche du coût de production. Cette tendance contraint les acteurs du marché à mettre en place de nouvelles solutions moins onéreuses. Parmi les recherches dans ce domaine, la conception en vue du test (DfT) consiste à intégrer pendant le développement de la puce, une circuiterie additionnelle susceptible d'en faciliter le test, voire d'effectuer un auto-test (BIST). Mais la sélection d'une de ces techniques nécessite une évaluation de leur capacité de différencier les circuits fonctionnels des circuits défaillants. Ces travaux de recherche introduisent une méthodologie d'estimation de la qualité d'une DfT ou d'un BIST dans le flot de conception de circuits analogiques et mixtes. Basée sur la génération d'un large échantillon prenant en compte l'impact des variations d'un procédé technologique sur les performances et les mesures de test du circuit, cette méthodologie calcule les métriques de test exprimant la capacité de chaque technique de détecter les circuits défaillants sans rejeter des circuits fonctionnels et d'accepter les circuits fonctionnels en rejetant les circuits défaillant. Ensuite, le fonctionnement d'un auto-test numérique adapté aux convertisseurs sigma-delta est présenté ainsi qu'une nouvelle méthode de génération et d'injection du stimulus de test. La qualité de ces techniques d'auto-test est démontrée en utilisant la méthodologie d'estimation des métriques de test. Enfin, un démonstrateur développé sur un circuit programmable démontre la possibilité d'employer une technique d'auto-test dans un système de calibrage intégré.
153

Optimal source coding with signal transfer function constraints

Derpich, Milan January 2009 (has links)
Research Doctorate - Doctor of Philosophy (PhD) / This thesis presents results on optimal coding and decoding of discrete-time stochastic signals, in the sense of minimizing a distortion metric subject to a constraint on the bit-rate and on the signal transfer function from source to reconstruction. The first (preliminary) contribution of this thesis is the introduction of new distortion metric that extends the mean squared error (MSE) criterion. We give this extension the name Weighted-Correlation MSE (WCMSE), and use it as the distortion metric throughout the thesis. The WCMSE is a weighted sum of two components of the MSE: the variance of the error component uncorrelated to the source, on the one hand, and the remainder of the MSE, on the other. The WCMSE can take account of signal transfer function constraints by assigning a larger weight to deviations from a target signal transfer function than to source-uncorrelated distortion. Within this framework, the second contribution is the solution of a family of feedback quantizer design problems for wide sense stationary sources using an additive noise model for quantization errors. These associated problems consist of finding the frequency response of the filters deployed around a scalar quantizer that minimize the WCMSE for a fixed quantizer signal-to-(granular)-noise ratio (SNR). This general structure, which incorporates pre-, post-, and feedback filters, includes as special cases well known source coding schemes such as pulse coded modulation (PCM), Differential Pulse-Coded Modulation (DPCM), Sigma Delta converters, and noise-shaping coders. The optimal frequency response of each of the filters in this architecture is found for each possible subset of the remaining filters being given and fixed. These results are then applied to oversampled feedback quantization. In particular, it is shown that, within the linear model used, and for a fixed quantizer SNR, the MSE decays exponentially with oversampling ratio, provided optimal filters are used at each oversampling ratio. If a subtractively dithered quantizer is utilized, then the noise model is exact, and the SNR constraint can be directly related to the bit-rate if entropy coding is used, regardless of the number of quantization levels. On the other hand, in the case of fixed-rate quantization, the SNR is related to the number of quantization levels, and hence to the bit-rate, when overload errors are negligible. It is shown that, for sources with unbounded support, the latter condition is violated for sufficiently large oversampling ratios. By deriving an upper bound on the contribution of overload errors to the total WCMSE, a lower bound for the decay rate of the WCMSE as a function of the oversampling ratio is found for fixed-rate quantization of sources with finite or infinite support. The third main contribution of the thesis is the introduction of the rate-distortion function (RDF) when WCMSE is the distortion metric, denoted by WCMSE-RDF. We provide a complete characterization for Gaussian sources. The resulting WCMSE-RDF yields, as special cases, Shannon's RDF, as well as the recently introduced RDF for source-uncorrelated distortions (RDF-SUD). For cases where only source-uncorrelated distortion is allowed, the RDF-SUD is extended to include the possibility of linear-time invariant feedback between reconstructed signal and coder input. It is also shown that feedback quantization schemes can achieve a bit-rate only 0.254 bits/sample above this RDF by using the same filters that minimize the reconstruction MSE for a quantizer-SNR constraint. The fourth main contribution of this thesis is to provide a set of conditions under which knowledge of a realization of the RDF can be used directly to solve encoder-decoder design optimization problems. This result has direct implications in the design of subband coders with feedback, as well as in the design of encoder-decoder pairs for applications such as networked control. As the fifth main contribution of this thesis, the RDF-SUD is utilized to show that, for Gaussian sta-tionary sources with memory and MSE distortion criterion, an upper bound on the information-theoretic causal RDF can be obtained by means of an iterative numerical procedure, at all rates. This bound is tighter than 0:5 bits/sample. Moreover, if there exists a realization of the causal RDF in which the re-construction error is jointly stationary with the source, then the bound obtained coincides with the causal RDF. The iterative procedure proposed here to obtain Ritc(D) also yields a characterization of the filters in a scalar feedback quantizer having an operational rate that exceeds the bound by less than 0:254 bits/sample. This constitutes an upper bound on the optimal performance theoretically attainable by any causal source coder for stationary Gaussian sources under the MSE distortion criterion.
154

Fully Differential Difference Amplifier based Microphone Interface Circuit and an Adaptive Signal to Noise Ratio Analog Front end for Dual Channel Digital Hearing Aids

January 2011 (has links)
abstract: A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog front-end consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67u¬W from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA / Dissertation/Thesis / Ph.D. Electrical Engineering 2011
155

Silicon Carbide Sigma-Delta Modulatorfor High Temperature Applications

Tian, Ye January 2014 (has links)
<p>QC 20140609</p>
156

Récepteur radio-logicielle hautement numérisé / Highly digitized RF receiver for software defined radio

Haghighitalab, Delaram 09 September 2015 (has links)
Aujourd'hui, il y a une augmentation du nombre de normes étant intégré dans des appareils mobiles. Les problèmes principaux sont la durée de vie de la batterie et la taille de l'appareil. L'idée d'un Radio-Logiciel est de pousser le processus de numérisation aussi près que possible de l'antenne. Dans cette thèse, nous présentons la première mise en œuvre d'un récepteur radio-logiciel complet basé sur Sigma-Delta RF passe-bande, y compris un LNA à gain variable (VGLNA), un ADC Sigma-Delta RF sous-échantillonné, un mélangeur bas-conversion RF numérique et un filtre de décimation polyphasé multi-étage multi-taux. Le VGLNA élargit la gamme dynamique du récepteur multi-standard pour atteindre les exigences des trois normes sans fil ciblées. Aussi une architecture mixte, en utilisant à la fois Source-Coupled Logic (SCL) et des circuits CMOS, il est proposé d'optimiser la consommation des circuits RF numériques. Par ailleurs, nous proposons une architecture de filtre en peigne à plusieurs étages avec décomposition polyphase à réduire la consommation d'énergie. Le récepteur est mesuré pour trois normes différentes dans la bande de 2.4 GHz, la bande ISM. Les résultats des mesures montrent que le récepteur atteint 79 dB, 73 dB et 63 dB de plage dynamique pour les normes Bluetooth, ZigBee et WiFi respectivement. Le récepteur complet, mis en œuvre dans le procédé CMOS 130 nm, a une fréquence centrale accordable de 300 MHz et consomme 63 mW sous 1.2 V. Comparé à d'autres récepteurs, le circuit proposé consomme 30% moins d'énergie, la plage dynamique est de 21 dB supérieur, IIP3 est de 6 dB supérieur et le facteur de mérite est de 24 dB supérieur. / Nowadays there is an increase in the number of standards being integrated in mobile devices. The main issues are battery life and the size of the device. The idea of a Software Defined Radio is to push the digitization process as close as possible to the antenna. Having most of the circuit in the digital domain allows it to be reconfigurable thus requiring less area and power consumption. In this thesis, we present the first implementation of a complete SDR receiver based on RF bandpass Sigma-Delta including a Variable-Gain LNA (VGLNA), an RF subsampled Sigma-Delta ADC, an RF digital down-conversion mixer and a polyphase multi-stage multi-rate decimation filter. VGLNA enlarges the dynamic range of the multi-standard receiver to achieve the requirements of the three targeted wireless standards. Also a mixed architecture, using both Source-Coupled Logic (SCL) and CMOS circuits, is proposed to optimize the power consumption of the RF digital circuits. Moreover, we propose a multi-stage comb filter architecture with polyphase decomposition to reduce the power consumption. The receiver is measured for three different standards in the 2.4 GHz ISM-band. Measurement results show that the receiver achieves 79 dB, 73 dB and 63 dB of dynamic range for the Bluetooth, ZigBee and WiFi standards respectively. The complete receiver, implemented in 130 nm CMOS process, has a 300 MHz tunable central frequency and consumes 63 mW under 1.2 V supply. Compared to other SDR receivers, the proposed circuit consumes 30% less power, the DR is 21 dB higher, IIP3 is 6 dB higher and the overall Figure of Merit is 24 dB higher.
157

High-temperature Bulk CMOS Integrated Circuits for Data Acquisition

Yu, Xinyu 07 April 2006 (has links)
No description available.
158

BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS

PATEL, VIPUL J. 02 October 2006 (has links)
No description available.
159

Impact des transformations algorithmiques sur la synthèse de haut niveau : application au traitement du signal et des images / Impact of algorithmic transforms for High Level Synthesis (HLS) : application to signal and image processing

Ye, Haixiong 20 May 2014 (has links)
La thèse porte sur l'impact d'optimisations algorithmiques pour la synthèse automatique HLS pour ASIC. Ces optimisations algorithmiques sont des transformations de haut niveau, qui de part leur nature intrinsèque restent hors de porter des compilateurs modernes, même les plus optimisants. Le but est d'analyser l'impact des optimisations et transformations de haut niveau sur la surface, la consommation énergétique et la vitesse du circuit ASIC. Les trois algorithmes évalués sont les filtres non récursifs, les filtres récursifs et un algorithme de détection de mouvement. Sur chaque exemple, des gains ont été possibles en vitesse et/ou en surface et/ou en consommation. Le gain le plus spectaculaire est un facteur x12.6 de réduction de l'énergie tout en maitrisant la surface de synthèse et en respectant la contrainte d'exécution temps réel. Afin de mettre en perspective les résultats (consommation et vitesse), un benchmark supplémentaire a été réalisé sur un microprocesseur ST XP70 avec extension VECx, un processeur ARM Cortex avec extension Neon et un processeur Intel Penryn avec extensions SSE. / The thesis deals with the impact of algorithmic transforms for HLS synthesis for ASIC. These algorithmic transforms are high level transforms that are beyond the capabilities of modern optimizing compilers. The goal is to analyse the impact of the High level transforms on area execution time and energy consumption. Three algorithms have been analyzed: non recursive filters, recursive filter and a motion detection application. On each algorithm, the optimizations and transformations lead to speedups and area/surface gains. The most impressive gain in energy reduction is a factor x12.6, while the area remains constant and the execution time smaller than the real-time constraint. A benchmark has been done on SIMD general purpose processor to compare the impact of the high level transforms: ST XP70 microprocessor with VECx extension, ARM Cortex with Non extension and Intel Penryn with SSE extension.
160

Porovnání použití přístrojových transformátorů a senzorů v aplikacích s ochranou REF 542plus / Comparison of Instrument Transformer and Sensor Applications in Feeder Terminal REF 542plus

Hrycík, Tomáš January 2010 (has links)
The aim of this Master´s thesis is use of instrument transformers and sensors on field of industry protection. We will compare current and voltage transformers, current sensor – based on Rogowski coil, voltage sensor – based on voltage divider. By this measure devices, we can monitoring values of analog quantities in medium voltage switchgear. It is impossible to compare, measure and analyze without this measure devices. There is protection terminal REF542plus, which can compile this values. The REF542plus ability are measuring, monitoring, remote control and protection. First, we will discuss about theory of sensors and convential instrument transformers and analysis of analog signal. We will compare analog input channel on sensor´s analog module and transformer´s analog module. There are few differences between type of analog modules. For analog signal analysis are important frequency filters and Analog/ Digital Convertor (sigma-delta). We will describe functions and options of REF542plus. In practical part of this project, we will test protection functions of protection terminal. First, protection terminal will be connected to sensors. Second protection terminal will be connected to transformers. For testing we chose Earth-fault directional protection and differential protection. We will make only secondary tests. That´s mean, input analog quantities to REF542plus will be simulated by tester. In all we will verify quality of protection. We will focus on lower settings of protection and we will inject protection by low current. Objectives are testing of trip characteristics and measuring of trip time.

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