The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator. The proposed Sigma Delta modulator uses TSMC 0.18£gm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.

Continuous-time sigma-delta modulator can be applied to wireless communications, photography and MP3 player. Portable electronics products became mainstream the design of a low power consumption analog circuit become important. Therefore, this paper presents a low power consumption continuous-time sigma-delta modulator. The low-power continuous-time sigma-delta modulator includes one-bit quantizer and a third-order loop filter consisting of resistor-capacitor integrators. Through the modified Z-transform, the discrete time loop filter design is transformed to the continuous time loop filter design. The proposed sigma-delta modulator used TSMC 0.18£gm CMOS 1P6M standard process, and its supply voltage is 1V, oversampling ratio is 32, bandwidth is 200 KHz, effective number is 13bit, power consumption is 1.5mW. Keywords: GSM, low power consumption, low power supply, continuous-time, sigma-delta modulator.

Continuous-time sigma-delta modulators play an important role in the development of biomedical sensors. It is suitable for monitoring of basic human vital functions (i.e., heartbeat and respiration). However, the physiological signal is very weak and it belongs to low-frequency range, the observed signals are strongly inter¬fered by the intrinsic flicker noise form CMOS transistors, which will cause a certain degree of difficulty in the identification. This thesis describes the implementation of loop filter using a differential chopper-stabilized configuration to reduce the influence of flicker noise on sigma-delta modulator within the signal bandwidth. The noise analysis of this sigma-delta modulator is calculated by the time-domain noise simulation. This method can take the noise factors into account when analyzing the overall performance. The proposed sigma-delta modulator is fabricated using TSMC 0.35£gm 2P4M CMOS technology. The chip area is 1.403 x 1.4 mm2. With a sampling rate of 20.8 kHz, the modulator achieves 84.4 dB of the peak SNDR and ENOB is 13.7-bit within signal band¬width of 10Hz. It dissipates 3.46 mW under 3V supply voltage.

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content.

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.

Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed.

A low voltage low power sigma¡Vdelta modulator for voice applications is presented. The implementation of proposed sigma-delta modulator is based on switched-capacitor circuit. Bootstrapped switches were used to replace CMOS transmission gates for increasing the insufficient driving of switched-capacitor circuit under the low voltage operation. To reduce the power dissipation, an improved current mirror OTA were designed with rail-to-rail output swing, which can also make the voltage gain enhance 10~20 dB and overcome the poor voltage gain shortage of traditional current mirror OTA. The post-simulation result shows that the modulator achieves a dynamic range of 77 dB, a peak signal-to-noise ratio of 82 dB, and the sigma-delta modulator dissipates 25£gW under 1.1-V voltage supply, using TSMC 0.18£gm 1P6M CMOS technology.

This thesis presents a novel three-level modulation technique for a Class-D audio amplifier, attempting to improve the poor performance of the conventional two-level modulation scheme at low input levels. The main drawback of the conventional two-level PWM (pulse-width modulation) and SDM (sigma-delta modulation) Class-D amplifier is that, with a zero input or small input, the excessively fast switching action at the output causes unwanted switching loss and switching noise, resulting in unnecessary energy waste and SNDR degradation. The presented three-level modulation circuit mainly consists of a linear feedback compensator, two comparators, and a switching logic circuit. The simulation and experimental results shows that the proposed three-level modulation s cheme outperforms the two-level sigma-delta modulation scheme in both efficiency and performance.

The systems which contain coarsely quantized signals are commonly found in applications where the actuators and/or sensors can only output a finite number of levels. This thesis focuses on the problem of synthesizing a finite-level control force for a certain control task, first presenting a systematic design method based on the theory of sliding modes and then applying it to the designs of the class-D audio amplifier and synchronous buck converter. At the first part, a novel three-level modulation technique for a class-D audio amplifier is designed by the sliding mode control theory. The simulated and experimental results conform to the excellent performance of this three-level modulation scheme. In particular, the proposed modulation scheme improves the poor efficiency of a conventional two-level class-D audio amplifier when the audio input signal is small, also excludes the output LC filter. The experiment shows that the designed three-level class-D amplifier achieves a minimum total harmonic distortion plus noise of 0.039% and an efficiency of 85.18%. At the second part, the controller of a synchronous buck converter is designed. The proposed self-oscillating controller stabilizes the buck converter in sliding mode, without the need of a triangular wave generator like the conventional PWM method. A 12V/1.5V synchronous buck converter with proposed control is built in the laboratory. The experiment shows 0.66% of the static output ripple and 3% of the load regulation error in response to the 15A step change of the load current at a slew rate of 50A/£gs.

In this thesis, a switched-current sigma-delta modulator (SDM) with op-amp active integrator is proposed. The major study is focused on using the op-amp to reduce the input impedance for high speed and high solution and utilizes the dummy switch to decrease the clock feedthrough (CFT) error. We use a sample-and-hold circuit which consists of an op-amp active memory cell and a dummy switch circuit to implement the integrator. It is applied to the building blocks of SDM. The modulator is a second order sigma-delta modulator. A current comparator transforms the current signal into digital voltage signal. A single-bit digital-to-analog (D/A) feedback circuit is used to convert the one-bit digital output to the SI integrator .The modulator is designed in the current mode technique. The delta-sigma modulator simulates using the parameters of the TSMC 0.35£gm CMOS process. The simulation results show that the signal to noise plus distortion ratio (SNDR) is 72 dB, the sampling rate is 10.24MHz, the oversampling ratio is 128, the power consumption is 21mW, the dynamic range is about 70dB, and the power supply is 3.3V. Furthermore, the circuit is verified by cadence-hspice simulation.