Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.

With a reference specification model in terms of 8 GS/s Sigma Delta Modulator in a 28 nm CMOS process consuming 890 mW, the purpose with this thesis is to construct a similar and simpler model but with higher specification demands. In a 22 nm SOI process with an input signal bandwidth of 500 MHz sampled at 16 GS/s with a power consumption below 2 W, the objective is to design a Continuous-Time Sigma Delta Modulator with verified simulated functionality on a transistor level basis. This specification is accomplished - with a power consumption in total of 75 mW. The design methodology is divided into an integrator part along with a quantizer and feedback DAC part. A top-down strategy is carried out starting with an ideal high level Verilog-A model for the complete system, followed by a hardware implementation on transistor level.

Three-Dimensional (3D) optical range-imaging is a field experiencing rapid growth, expanding into a wide variety of machine vision applications, most recently including consumer gaming. Time of Flight (ToF) cameras, akin to RADAR with light, sense distance by measuring the round trip time of modulated Infra-Red (IR) illumination light projected into the scene and reflected back to the camera. Such systems generate 'depth maps' without requiring the complex processing utilised by other 3D imaging techniques such as stereo vision and structured light. Existing range-imaging solutions within the ToF category either perform demodulation in the analogue domain, and are therefore susceptible to noise and non-uniformities, or by digitally detecting individual photons using a Single Photon Avalanche Diode (SPAD), generating large volumes of raw data. In both cases, external processing is required in order to calculate a distance estimate from this raw information. To address these limitations, this thesis explores alternative system architectures for ToF range imaging. Specifically, a new pixel concept is presented, coupling a SPAD for accurate detection of the arrival time of photons to an all-digital Phase- Domain Delta-Sigma (PDΔΣ) loop for the first time. This processes the SPAD pulses locally, converging to estimate the mean phase of the incoming photons with respect to the outgoing illumination light. A 128×96 pixel sensor was created to demonstrate this principle. By incorporating all of the steps in the range-imaging process – from time resolved photon detection with SPADs, through phase extraction with the in-pixel phase-domain ΔΣ loop, to depth map creation with on-chip decimation filters – this sensor is the first fully integrated 3D camera-on-achip to be published. It is implemented in a 130nm CMOS imaging process, the most modern technology used in 3D imaging work presented to date, enabled by the recent availability of a very low noise SPAD structure in this process. Excellent linearity of ±5mm is obtained, although the 1σ repeatability error was limited to 160mm by a number of factors. While the dimensions of the current pixel prevent the implementation of very high resolution arrays, the all-digital nature of this technique will scale well if manufactured in a more advanced CMOS imaging process such as the 90nm or 65nm nodes. Repartitioning of the logic could enhance fill factor further. The presented characterisation results nevertheless serve as first validation of a new concept in 3D range-imaging, while proposals for its future refinement are presented.

Recently short word-length (normally 1 bit or bits) processing has become a promising technique. However, there are unresolved issues in sigma-delta modulation, which is the basis for 1b/2b systems. These issues hindered the full adoption of single-bit techniues in industry. Among these problems is the stability of high-order modulators and the limit cycle behaviour. More importantly, there is no adaptive LMS structure of any kind in 1b/2b domain. The challenge in this problem is the harsh quantization that prevents straightforward LMS application. In this thesis, the focus has been made on three axes: designing new single-bit DSP applications, proposing novel approaches for stability analysis, and tacking the unresolved problems of 1b/2b adaptive filtering. Two structures for 1b digital comb filtering are proposed. A ternary DC blocker structure is also presented and performance is tested. We also proposed a single-bit multiplierless DC-blocking structure. The s tability of a single-bit high-order signma-delta modulator is studied under dc inputs. A new approach for stability analysis is proposed based on analogy with PLL analysis. Finally we succeeded in designing 1b/2b Wiener-like filtering and introduced (for the first time) three 1b/2b adaptive schemes.

Short Word-Length refers to single-bit, two-bit or ternary processing systems. SWL systems use Sigma-Delta Modulation (SDM) technique to express an analogue or multi-bit input signal in terms of a high frequency single-bit stream. In Sigma-Delta Modulation, the input signal is coarsely quantized into a single-bit representation by sampling it at a much higher rate than twice the maximum input frequency viz. the Nyquist rate. This single-bit representation is almost exclusively filtered to remove conversion quantization noise and sample decimated to the Nyquist frequency in preparation for traditional signal processing. SWL algorithms have a huge potential in a variety of applications as they offer many advantages as compared to multi-bit approaches. Features of SWL include efficient hardware implementation, increased flexibility and massive cost savings. Field Programmable Gate Arrays (FPGAs) are SRAM/FLASH based integrated circuits that can be programmed and re-programmed by the end user. FPGAs are made up of arrays of logic gates, routing channels and I/O blocks. State-of-the-art FPGAs include features such as Advanced Clock Management, Dedicated Multipliers, DSP Slices, High Speed I/O and Embedded Microprocessors. A System-on-Programmable-Chip (SoPC) design approach uses some or all the aforementioned resources to create a complete processing system on the device itself, ensuring maximum silicon area utilization and higher speed by eliminating inter-chip communication overheads. This dissertation focuses on the application of SWL processing systems in audio Class-D Amplifiers and aims to prove the claims of efficient hardware implementation and higher speeds of operation. The analog Class-D Amplifier is analyzed and an SWL equivalent of the system is derived by replacing the analogue components with DSP functions wherever possible. The SWL Class-D Amplifier is implemented on an FPGA, the standard emulation platform, using VHSIC Hardware Description Languages (VHDL). The approach is taken a step forward by adding re-configurability and media selectivity and proposing SDM adaptivity to improve performance.

De nos jours, les systèmes de communications supportent un nombre croissant de normes radios dont les exigences en termes de bande et de vitesse sont diverses. Ceci rend la conception d'un convertisseur analogique numérique (CAN) unique convenant à toutes ces normes, une tache très problématique. La reconfigurabilité est une solution à ce problème, où la résolution serait échangée contre la bande passante. Les CANs Sigma Delta offrent un moyen facile d'effectuer cet échange en ajustant leur rapport de sur-échantillonnage. Cependant, ils ne sont adaptés pour les applications larges bandes. La parallélisation des CANs Sigma Delta surmonte ce problème et en plus augmente la reconfigurabilité du CAN. Dans ce travail, la conception d'un CAN Sigma Delta reconfigurable et parallèle est présentée. Sa reconfigurabilité permet de faire des échanges entre bande de conversion et résolution ainsi qu'entre consommation de puissance et bande de conversion. Ceci est possible grâce à un contrôle sur le nombre actifs de canaux, sur le rapport de sur-échantillonnage, sur la fréquence d'opération et sur l'ordre des modulateurs. Une nouvelle technique d'interpolation est également proposée. Elle permet de réduire les tailles des capacités et les contraintes sur le filtre anti-repliement. Un prototype du CAN a été fabriquée dans une technologie CMOS 65 nm. Il a été conçu pour satisfaire les exigences des normes GSM, UMTS, EDGE, DVB-T, WiFi et WiMax. Pour le scénario GSM/EDGE, le CAN a une résolution de 13 bits pour une consommation de 1.74 mW. Pour le reste des scénarios, les performances visées ne sont pas atteintes cependant la fonctionnalité a été testée avec succès.

<p> </p><p>I detta examensarbete har metoder för design av en FPGA-baserad PCM-till-PWM-modulator för klass D-audioförstärkare testats och utvärderats. Rapporten diskuterar med stöd av matematisk analys och simuleringar interpoleringsmetoder, pulsbreddsmodulering, samplingsprocesser och sigma-delta-modulatorer. Den föreslagna designen bygger på uppsampling, förkompensering, brusformning och pulsbreddsmodulering. Designens prestanda har verifierats genom simulering av modell och implementering i hårdvara.</p><p> </p> / <p> </p><p>This thesis experiments and evaluates methods for design of an FPGA based PCM-to-PWM modulator to be used in a class D audio amplifier. By utilizing mathematical analysis and simulations interpolation methods, pulse width modulation, cross point derivers and sigma delta modulators are discussed. The proposed design consists of upsampling, predistortion, noise shaping and pulse width modulation. The design has been validated through model based simulation and implementation in hardware.</p><p> </p>

<p>Today the frequency spectrum is full of wireless standards. The most common technique being used is the frequency modulation. To take advantage of this and the technology improvement a new wireless communication standard is being developed. This standard is using a low power impulse modulation method, allowing it to overlap with other standards. The proposed standard called IEEE802.15.3a is applied at an Ultra Wide Band and has potential to be used both in interchip and intrasystem communication, since it allows a very high data density. </p><p>In this thesis the analog to digital converter is designed, which is one part of a communication system. Although the signal bandwidth is very wide the converter is designed as a Sigma-Delta modulator, which is most suitable for low-speed applications. Its main advantages over high-speed converters are less area and less power consumption. The goal of this project is to investigate if the CMOS090 process technology will be sufficient for reaching a signal-to-noise ratio, SNR, of 30 dB in a signal band of 264 MHz. </p><p>The main limiting factor during the design of the modulator is the excess feedback delay. This delay degrades the SNR and can even make the system unstable. At a feedback delay of 83 ps and a sampling frequency of 6.336 GHz, the maximum SNR achieved was 27 dB. At this high frequency the modulator is close to instability. Hence, to ensure stability a maximum sampling frequency of 4.224 GHz is chosen, achieving a SNR of 19 dB. </p><p>The effect of the feedback delay can be reduced either by using a different structure or by using compensation methods, either of them would probably allow a SNR above 30 dB.</p>

<p>The development of integrated circuit technology seen in the last decades has enabled a large variety of battery operated equipment to emerge, such as smallsensors and medical implants. These applications often has low requirements on sampling frequency but require a very low power consumption to achieve a longbattery life.</p><p>This thesis investigates one aspect of implementing a low power and low frequency analog to digital converter (ADC) using a technique called Sigma Delta-modulation.The Sigma Delta-ADC uses few analog components but instead it requires a digital filter to extract the wanted resolution. It is this filter which is under investigation in this work.</p><p>To investigate the power consumption under the presumption that the filter would be a custom circuit implemented on-chip, a simplistic approach has been taken. Based on a high-level algorithmic investigation and the fact that it is popularly used together with Sigma Delta-modulators the Cascaded Integrator Comb (CIC) filter was chosen for implementation.</p><p>The CIC-filter uses only adders and delay elements which is a great advantage when aiming at a low power consumption. The drawback is that this filter has a poor passband which can introduce distortion within the signal band. Using the Spectre simulator provided in the Cadence Virtuoso suite the lowest power consumption achieved was 16 nW, extracting 80 % of the theoretically available resolution.</p>

<p>In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.</p><p>The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.</p>