Thesis (M.S.)--Missouri University of Science and Technology, 2009. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 16, 2009) Includes bibliographical references (p. 90-91).

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Thesis (M.S.)--Oregon State University, 2010. / Printout. Includes bibliographical references (leaves 74-76). Also available on the World Wide Web.

Thesis (M.S.)--Missouri University of Science and Technology, 2009. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 17, 2009) Includes bibliographical references (p. 61-62).

As the ever-advancing fabrication technologies in semiconductor industry enable the VLSI circuits with increasing integration and decreasing cost, the circuits suffer from much severer Signal Integrity (SI) faults, where SI is the capability of signals generating correct responses in their downstream circuits. SI faults are complex problems to tackle since SI may be damaged by numerous kinds of causes and SI faults may impact multiple aspects of circuits' performance. Such SI problems can seriously reduce product yield, result in function error or even permanently damage the chip. Therefore, effective testing methodologies are essential to alleviate SI problems by verifying the SI satisfaction of VLSI circuits efficiently. / Hereby the thesis has examined the SI problems systematically and proposed effective test methods corresponding to the specific feature of SI faults. Firstly, considering that SI on inter-core interconnects of SOCs is under severe danger, new test wrapper design has been proposed to achieve accurate SI test on interconnects. Secondly, test architecture has been optimized for cost reduction considering SI test and logic test simultaneously. Thirdly, the impact of power distribution network (PDN) defects on SI has been analyzed and efficient computation method has been proposed to identify those potentially harmful PDN defects. Effective test pattern manipulation method has also been proposed to improve test coverage of PDN defects. Fourthly, considering the increasing impact of process variation and aging effect on SI, an innovative online test architecture has been proposed, which can accurately measure the delay of critical paths when the circuit is working in function mode, where such valuable information is of great help for a variety of applications. / Zhang, Yubin. / Adviser: Qiang Xu. / Source: Dissertation Abstracts International, Volume: 73-06, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 121-133). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

This dissertation proposed two time-domain algorithms for extracting the broadband SPICE-compatible models of high-speed coupled interconnects. The first approach is proposed to synthesized the equivalent models of multi-conductor interconnects by cascading multiple configuration-oriented coupled transmission line (CCTL) units. The second approach focuses on the modeling of differential via based on a broadband macro-£k model with three modules represented by the optimum pole-residue forms. Using a systematic lumped-model extraction technique (SLET), all the pole-residue rational functions can transfer into a corresponding lumped model. The accuracy of the two algorithms is demonstrated both in time- and frequency -domain responses comparison with the direct 3D-FDTD simulation.

In this thesis, we study the discontinuity structure electromagnetic effect of multilayer printed circuit board in three sections. In first section, we introduced a modeling approach which is based on transmission line theory , and simulated with a series of test boards ,such as regular and irregular power delivery system and multilayer with via structure, finally ,we confirmed that the modeling approach is an efficient simulation and agreed fairly well with 3D full-wave method. In second section, we demonstrated the return current is disrupted at the via or broken at the power / ground plane with slots , the impedance becomes extremely high at the resonance frequencies of the power / ground plane cavity and via could be a major cause of the simultaneous switching noise generation, signal quality problem, and edge radiated emission in multi-layer PCB. In final section, we provided a effective reduction mechanism to eliminate the noise or EMI, which has been achieved using island with shorting vias and combining with the modeling approach can simulate and estimate effectively.

In a wireless communication system, the RF signal integrity is often deteriorated by power amplifier (PA) nonlinearity and local oscillator (LO) pulling. This dissertation attempts to study power amplifier and local oscillator with the deliberate input distortion or interference for understanding, and hence improving, the resultant RF signal integrity issues. Furthermore, the scope of this study is extended to explore novel wireless applications. Based on the above thoughts, this dissertation includes three topics. The first topic is devoted to a baseband digital predistortion technique for enhancing the power amplifier linearity in a wireless RF transmitter. A digital predistorter has been designed to compensate the amplitude and phase distortion due to the nature of PAs, and the predistortion can enhance the linearity of linear PAs as well as switching-mode PAs. The second topic proceeds with a rigorous analysis of a local oscillator subject to injection signal. A phase-locked loop (PLL) under injection is analyzed in frequency domain to account for the inherent band-pass filtering on an injection signal. Such analysis can further predict the effect of co-frequency or co-channel interference on the PLL phase noise. A discrete-time analysis is also provided to predict output spectra of the LO pulled by a sinusoidal and modulated injection signal. The final topic presents a novel RF sensing circuit for a cognitive radio to sense spectral environment using injection locking and frequency demodulation techniques. The proposed RF sensing circuit can fast and reliably detect frequency and power for analog and digital modulation signals. In addition, the sensing principle and circuit architecture are delivered on theoretical basis developed in this dissertation. A discrete time approach is also investigated to compute the sensed output signal.

Advancements in very large scale integration (VLSI) technology have led to unprecedented transistor and interconnect scaling. Further miniaturization by traditional IC scaling in future planar CMOS technology faces significant challenges. Stacking of ICs (3D IC) using three dimensional (3D) integration technology helps in significantly reducing wiring lengths, interconnect latency and power dissipation while reducing the size of the chip and enhancing performance. Interposer technology with ultra-fine pitch interconnections needs to be developed to support the huge I/O connection requirement for packaging 3D ICs. Through vias in stacked silicon ICs and interposers are the key components of a 3D system. The objective of this dissertation is to model through vias in 3D silicon and glass interposers and, to address power and high-speed signal integrity issues in 3D interposers considering silicon biasing effects. An equivalent circuit model of the through via in silicon interposer (Si TPV) has been proposed considering the bias voltage dependent Metal-Oxide-Semiconductor (MOS) capacitance effect. Important design guidelines and optimizations are proposed for Si TPVs used in the signal delivery network, power delivery network (PDN), and as variable capacitors. Through vias in glass interposers (Glass TPVs) are modeled, designed and simulated by using electromagnetic field solvers. Signal and power integrity analyses are performed for silicon and glass interposers. PDN design is proposed by utilizing the MOS capacitance of the Si TPVs for decoupling.

In contemporary communication systems, Digital-to-Analog Converters (DAC), Signal Defined Radio (SDR) signal creation, and clock data recovery are essential components. DACs convert digital signals to analog signals, creating continuous waveforms. DACs provide versatility in the transmission of SDR by supporting a range of communication protocols. Clock data recovery enables precise signal recovery and synchronization at the receiver end. These elements work together to provide effective and high-quality communication systems across several sectors. With the development of quantum computing, these SDR systems also find extensive use in generating precisely timed signals for controlling components of a quantum computer and also for read-out operations from various specialized instruments. This thesis demonstrates an FPGA (Xilinx vcu118) with a DAC (Analog Devices AD9081) platform. It employs SDR for generating of periodic signals and also stream of bits which are then recovered using a simple Clock Data Recovery technique. The signal integrity of the generated signals and error-rate from the proposed Clock Data Recovery technique is also analyzed. / Master of Science / Communication systems in our networked world depend on key technologies to provide dependable connectivity. By converting digital data into continuous waveforms, Digital-to- Analog Converters (DACs) serve a crucial role in enabling the generation of various analog signals. This makes it possible for Software-Defined Radio (SDR) to produce a variety of modulated signals and enables smooth communication between various hardware and software systems. The Clock and Data Recovery (CDR) algorithms correct for clock fluctuations and phase offsets to provide precise signal recovery and synchronization. Together, these technologies improve communication networks' effectiveness and dependability, allowing seamless connectivity and enhancing our networked experiences. This thesis presents an SDR platform comprising Xilinx FPGA vcu118 and Analog Devices high-speed DAC/ADC AD9081. A CDR algorithm is also proposed to recover data from the signals generated by the DAC, and its effectiveness and error rate is also analyzed.