The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling. The optimization technique for selection and placement of decoupling capacitors uses a genetic algorithm (GA) and the multilayer finite element method (MFEM), a PDN modeling method using FEM. The GA is customized for the decoupling problem to enhance the convergence speed of the optimization. The mathematical modifications necessary for the incorporation of the capacitor model into MFEM is also presented. The main contribution of this dissertation is the development of a new modeling method, the multilayer triangular element method (MTEM), for power/ground planes of a PDN. MTEM creates a surface mesh on each plane-pair using dual graphs; a non-uniform triangular mesh (Delaunay triangulation) and its orthogonal counterpart (Voronoi diagram), to which electromagnetic and equivalent circuit concepts are applied. The non-uniform triangulation is especially efficient for discretizing multidimensional and irregular geometries which are common in package and board PDNs. Moreover, MTEM generates a sparse, banded, and symmetric system matrix, which enables efficient computations. For a given plane-pair, MTEM extracts an equivalent circuit that is consistent with the physics-based planar-circuit model of a plane-pair. Thus, the values of the lumped elements can be simply calculated from the physical parameters, such as material properties and mesh geometries of each unit-cell. Consequently, the modeling of MTEM is flexible and easy to modify for further extensions, such as the incorporation of external circuits, e.g. decoupling capacitors and vertical interconnects. Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the discontinuity, return currents have to detour or switch to different layers, causing signal and power integrity problems. Therefore, a separate analysis of signal interconnects will neglect the significant coupling with a PDN, and the result will not be reliable. In this dissertation, the co-simulation of the signal and power integrity is presented focusing on the modeling of RPDs created by split planes, apertures, and vias. Plane resonance is one of the main sources of power integrity problems in package and board PDNs. A number of techniques have been developed and published in literature to reduce or prevent the resonance of a plane-pair. One of the techniques is to surround plane-pair edges with absorbing material that effectively damps the outgoing parallel-plate wave and minimizes the reflection. To model this behavior, the boundary condition of MTEM needs to be changed from its original form, the open-circuit boundary condition. In this dissertation, the application of the 1st order absorbing boundary condition to MTEM is presented.

This dissertation is aimed at examining signal integrity degradation factors and realizing signal integrity enhancement circuits for both wired and wireless communication systems. For wired communication systems, an optical coherent system employing an electrical equalization circuit is studied as a way of extending the transmission distance limited by optical fiber dispersion mechanisms. System simulation of the optical coherent receiver combined with the feed-forward equalizers is performed to determine the design specification of the equalizer circuit. The equalization circuit is designed and implemented in a 0.18 µm complementary metal-oxide semiconductor (CMOS) process and demonstrates the capability to extend the transmission reach of long-haul optical systems over single-mode fiber to 600 km. Additionally, for wireless applications, signal integrity issues found in a full-duplex wireless communication network are examined. Full-duplex wireless systems are subject to interference from their own transmitter leakage signals; thus, a transmitter leakage cancellation circuit is designed and implemented in a 0.18 µm CMOS technology. The proposed cancellation circuit is integrated with a low-noise amplifier and demonstrates over 20 dB of transmitter leakage signal suppression.

The development of modern digital communication systems has been entered a new era with faster signal transmission and processing capability, called high-speed circuit systems. As their clock frequencies have increased and rise times of signals have decreased, the signal integrity of interconnects in the packaging and printed circuit boards plays a more and more important role. In high-speed circuit systems, the well-designed logic functions most likely will not work well if their interconnects are not taken into account.This dissertation addresses to profoundly understand the signal integrity knowledge, be proficient in calculation, simulation and measurements, and be capable of solving related signal integrity problems. The research mainly emphasizes on three aspects. First of all, the impact of on-wafer calibration methods on the measured results of coplanar waveguide circuits is comprehensively investigated, with their measurement repeatability and accuracy. Furthermore, a method is presented to characterize the physically-consistent broadband material properties for both rigid and flexible dielectric materials. Last but not least, a hybrid method for efficient modeling of three dimensional via structures is developed, in order to simplify the traditional 3D full-length via simulations and dramatically reduce the via build and simulation time and complexity.

La miniaturisation des circuits intégrés permet d'avoir une intégration plus élevée dans une même puce. Cela, conduit a des problèmes de qualité dans les signaux de communication et d’alimentation comme le phénomène de bruit de diaphonie entre les interconnections (Crosstalk) et de bruit dans le lignes d'alimentation (PSN, GB). Aussi problèmes de fiabilité peuvent éventuellement arriver a cause des variations dans les paramètres technologiques pendant le processus de fabrication. De ce fait, tout ces phénomènes ont un effet négatif sur le délai dans les circuits embarques (IC) et donnent lieu aux défauts sur le retard. Des échecs relie au délai dans les dispositifs semi conducteurs causes une augmentation de taux d'évasion de défaut, une perte de rendement et une diminution dans le taux de fiabilité. Techniques de Design-For-Test ont était développée a fin d'avoir une meilleur contrôlabilité et observabilité dans les nœuds internes du circuit pour détecter et localiser facilement l’emplacement des défauts. Cependant, ils ne sont pas toujours détectés par les modèles de défauts traditionnels.Cette thèse s’intéresse a l’analyse de ces phénomènes a fin de proposer de nouvelle méthodes de test du délai en considérant les phénomènes physiques pour faire face aux défauts provenant du processus de fabrication ou de problèmes physiques. Ces méthodes comprennent l'analyse de la variation du retard d'un chemin en présence du bruit de diaphonie, du bruit d'alimentation, et les variations de processus. Additionnellement, nous développons méthodes d'essai de retard sur un chemin pour identifier les motifs de test qui peuvent causer le pire des cas de retard sur un chemin cible. Les méthodes proposées peuvent être utilisées pour caractériser la vitesse de chemin et il contribue à résoudre le problème de «speed binning». En outre, ils peuvent être utilisés dans l'amélioration de l'approche classique ATPG de génération de «patterns» et elles sont indépendantes de la technologie. L'application de ces contributions peut apporter des améliorations considérables à la qualité de test IC en assurant une meilleure couverture des défauts et en aidant à augmenter le rendement de fabrication au cours de la vitesse du «binning» dans les puces IC. L’évolution en continue de la technologie en échelle nanométrique / Advancing nanometer technology scaling enables higher integration on a single chip with minimal feature size. As a consequence, the effects of signal and power integrity issues such as crosstalk noise between interconnects, power supply noise and ground bounce in the supply networks significantly increases. Also, reliability issues are eventually introduced by variations in the manufacturing process. These issues will negatively impact the timing characteristics in an integrated circuit (IC), as they give rise to delay defects. Delay-related parametric failures increase the defect escape rate, yield loss and diminish reliability rate. Hence, design-for-test techniques are employed to have a better controllability and observability on the internal nodes to easily detect and locate the faults. However, they are not always detected by the traditional fault models. In our work, we target these challenges and propose novel physical design-aware path delay test methods to deal with delay faults coming from manufacturing defects or physical design issues. They include the investigation of path delay variations in the presence of crosstalk noise, power supply noise, ground bounce and process variations. Based on this, we develop technology independent test methods for identifying the test patterns that may cause a worst-case delay on a target path. Then, we develop a dedicated test pattern generation method for path delay testing in the presence of crosstalk noise, power supply noise and ground noise. The proposed methods can be used to characterize the path speed and it helps to address the speed binning problem. Also, they can be employed in improving the classical ATPG approach of pattern generation. The application of these contributions can bring tremendous improvements to the IC test quality by ensuring better defect coverage and for an increased manufacturing yield during speed binning of IC chips.

Simulering är en viktig del av utvecklingsarbetet för nya datorkort hos Centre of Excellence - Computers på Saab AB i Jönköping. Ju tidigare i utvecklingsarbetet som defekter och svagheter hos designen hittas desto enklare och mindre kostsamma blir ändringarna att införa. På CoE används simulerings och analysverktyget HyperLynx från Mentor Graphics för att simulera alla kritiska nät. På så sätt kan svagheter hos en design hittas redan innan prototypstadiet. För att simulatorn ska vara användbar krävs dock en kunskap om hur dess resultat korrelerar med verkligheten. Det leder till den övergripande frågeställningen för detta arbete, hur väl överensstämmer HyperLynx simuleringsresultat med verkligheten? Frågeställningen besvarades genom att jämföra simuleringsresultat med motsvarande uppmätta signaler på ett testkort. Resultaten visar att HyperLynx håller en mycket god kvalitet. För signalen i helhet överensstämmer kurvformerna väl både när det gäller vilka reflektioner som bildas och timingen för reflektionerna. Enda genomgående skillnaden mellan simuleringarna och mätningarna visar på något för små amplituder för de simulerade reflektionerna. / Simulations are an important part of the process of designing new computer boards at the Centre of Excellence - Computers at Saab AB in Jönköping. The earlier problems and weaknesses in the design can be found during the design process the less time and money it will take to fix them. The engineers at CoE uses HyperLynx, an analysis and simulation software from Mentor Graphics, to simulate all the critical nets at the board. By doing so, the majority of the problems can be fixed before the prototyping stage. However, the engineers need to know how the simulated signals relate to real signals if the simulator is to be useful. Therefore the question to be answered in this study is how well does the simulated signals in HyperLynx imitate real signals? The question was answered by comparing simulated signals with measurements of corresponding signals on a test board. Overall the shapes of the signals are matching for both which reflections occurs and the timing of the reflections. The only noticeable difference found throughout the study is a slightly smaller amplitude of the reflections for the simulated signals compared to the corresponding measured signal. Due to these results, HyperLynx can be considered a high quality simulator.

The way printed circuit board interconnects for high-speed digital signals are designed ultimately determines the performance that can be achieved for a certain interface, thus having a profound impact on whether the complete communication channel will comply with the desired standard specification or not. Good understanding and methods for anticipating and verifying this behaviour through computer simulations and practical measurements are therefore essential. Characterization of an interconnect can be performed either in the time domain or in the frequency domain. Regardless of the domain chosen, a method for unobstrusively connecting to the test object is required. After various different attempts it could be concluded that frequency domain measurements using a vector network analyzer together with microwave probes will provide the best measurement fidelity and ease of use. In turn, this method requires the test object to be prepared for the measurement. Advanced computer simulation software is available, but comes with the drawback of dramatically increasing the requirements on computational resources for improved accuracy. In general, these simulators can be configured to show good agreement with measurements at frequencies as high as ten gigahertz. For ideal interconnects, the simplest and, thus, fastest methods will provide good enough accuracy. These simple methods should be complemented with the results from more accurate simulations in cases where the physical structure is complex or in other ways deviates from the ideal. Several practical routing situations were found to introduce severe signal integrity issues. Through appropriate use of the methods developed in this thesis, these can be identified in the design process and thereby avoided.

As the complexity of interconnects and packages increases and the rise and fall time of the signal decreases, the electromagnetic effects of distributed passive devices are becoming an important factor in determining the performance of gigahertz systems. The electromagnetic behavior extracted using an electromagnetic simulation or from measurements is available as frequency dependent data. This information can be represented as a black box called a macromodel, which captures the behavior of the passive structure at the input/output ports. In this dissertation, the macromodels have been categorized as scalable, passive and broadband macromodels. The scalable macromodels for building design libraries of passive devices have been constructed using multidimensional rational functions, orthogonal polynomials and selective sampling. The passive macromodels for time-domain simulation have been constructed using filter theory and multiport passivity formulae. The broadband macromodels for high-speed simulation have been constructed using band division, selector, subband reordering, subband dilation and pole replacement. An automated construction method has been developed. The construction time of the multiport macromodel has been reduced. A method for reducing the order of the macromodel has been developed. The efficiency of the methods was demonstrated through embedded passive devices, known transfer functions and distributed interconnect networks.

With the enormously developing of the wireless communication technology, the electromagnetic environment exposing to the electrical devices is becoming more and more complex. Besides, the trends of designing high-speed digital computer systems are toward fast edge rates, high clock frequencies, and low voltage levels. The electromagnetic susceptibility (EMS) or immunity of the high-speed circuit has become an important issue today apparently. In this thesis, we will firstly establish the measurement environment and calibration technology for numerical validation. Then we employ the three-dimension finite-differential time-domain (3D-FDTD) numerical method compared to the finite element method (FEM) to simulate the EMS behavior of the power delivery network (PDN) and traces of the printed circuit boards (PCB). In addition to several types of layout of the traces studied in this thesis, we also explain the mechanism and phenomenon of the EMS of the power/ground planes of the PCB. Besides the EMS behavior research of the traditional solutions to suppress the power noise, we propose an electromagnetic bandgap structure (EBG) which has the broadband suppression of the power noise and is validated to be effective to improve the EMS problems. Finally, we also propose a novel concept to increase the signal integrity (SI) by shielding design.

In this thesis, we study the electromagnetic effect of the high-speed digital PCB in three sections. In first section, based on the FDTD modeling approach, the bridging effect of the isolation moat on the EMI caused by the ground bounce noise is investigated. We find that isolating the noise source by slits is effective to eliminate the EMI, but bridges connecting between two sides of the slits will significantly degrade the effect of EMI protection. In second section, we investigate both in time and frequency domains the power plane noise coupling to signal trace with via transition in multi-layered PCB. Separating the power plane with slits is effective in reducing noise coupling in high frequency but a new resonant mode will be excited at lower frequency. Current distribution pattern of this new resonant mode between the power planes helps us to understand this phenomenon more clearly. In final section, by using FDTD link SPICE method, we can predict the electromagnetic behavior of the PCB with active device effectively.

In this dissertation, a new signaling scheme known as Constant Voltage Power Transmission Line (CV-PTL) is presented to supply power to a digital I/O circuit. This signaling scheme provides power through a transmission line in place of a power plane while dynamically changing the impedance of the power delivery network to keep a constant voltage at the power pin of the IC. Consequently, this reduces the effects of return path discontinuities and can improve the quality of output signal by reducing power and ground bounce. Through theory, simulation, and measurements, we show that this new method can be used to reduce jitter and eye height with the proposed PDN methodology. In addition, the signaling scheme was extended to vertically-stacked 3D integrated circuits (3D ICs). It is known that power supply noise worsens as one goes higher up in the stack of dies due to increased interconnect inductance. However, by utilizing the CV-PTL concept in the PDN design of a 3-layer 3DIC system, the circuit showed considerable improvement in power supply noise and peak-to-peak jitter as compared to the conventional design approach. In addition to signal and power integrity of these signaling schemes, the noise coupling between digital and RF components is also investigated. A simple design for mitigating the coupling of power supply noise in mixed-signal electronics is presented. Currently used methods, such as electromagnetic bandgap structures have been shown to exhibit excellent noise isolation characteristics, and are a popular area of research in this area. However, these structures can pose difficulties for signal integrity. The proposed method extends the previous power transmission line work to address both the power supply noise generation and isolation. Test vehicles using these proposed methods, as well as using an EBG structure were fabricated and tested with regards to power supply noise, jitter, and noise isolation. The proposed methods show significant improvements in almost all performance metrics as compared to EBG. Finally, this dissertation discusses the effect of implementing a power transmission line in a power distribution network composed of a switching regulator and a voltage regulator module. The DC conductor losses of the PTL can not only affect power efficiency of the entire system, but can also affect the proper operation of the linear regulator module when supporting large currents. Consequently, recommendations are made on the design of the PTL to ensure proper operation and efficiency.