M.Ing. (Electrical and Electronic Engineering) / With all the talk about the Information Highway and its construction, there is also a channel which is highly underestimated and thus almost ignored. On normal FM radio transmissions extra bandwidth exists, suitable for the transmission of audio and data. In this thesis the effects of interference on data transmission over the Supplementary Signal Transmission (SST) channel are analysed. The channel is characterized in terms of the Bit Error Rate (BER) versus field strength and distance from a transmitter ...

Wireless devices in wireless networks are powered typically by small batteries that are not replaceable nor recharged in a convenient way. To prolong the operating lifetime of networks, energy efficiency is indicated as a critical issue and energy-efficient resource allocation designs have been extensively developed. We investigated energy-efficient schemes that prolong network operating lifetime in wireless sensor networks and in wireless relay networks. In Chapter 2, the energy-efficient resource allocation that minimizes a general cost function of average user powers for small- or medium-scale wireless sensor networks, where the simple time-division multiple-access (TDMA) is adopted as the multiple access scheme. A class of Ç-fair cost-functions is derived to balance the tradeoff between efficiency and fairness in energy-efficient designs. Based on such cost functions, optimal channel-adaptive resource allocation schemes are developed for both single-hop and multi-hop TDMA sensor networks. In Chapter 3, optimal power control methods to balance the tradeoff between energy efficiency and fairness for wireless cooperative networks are developed. It is important to maximize power efficiency by minimizing power consumption for a given quality of service, such as the data rate; it is also equally important to evenly or fairly distribute power consumption to all nodes to maximize the network life. The optimal power control policy proposed is derived in a quasi-closed form by solving a convex optimization problem with a properly chosen cost-function. To further optimize a wireless relay network performance, an orthogonal frequency division multiplexing (OFDM) based multi-user wireless relay network is considered in Chapter 4. / In the OFDM approach, each subcarrier is dynamically assigned to a source- destination link, and several relays assist communication between pairs of source-destination over their assigned subcarriers. Using a class of Ç-fair cost-functions to balance the tradeoff between energy efficiency and fairness, jointly with optimal subcarrier and power allocation schemes at the relays. Relevant algorithms are derived in quasi-closed form. Lastly, the proposed energy-efficient schemes are summarized and future work is discussed in Chapter 5. / by Di Wang. / Thesis (Ph.D.)--Florida Atlantic University, 2011. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2011. Mode of access: World Wide Web.

High data rate acoustic communications become feasible with the use of communication systems that operate at high frequency. The high frequency acoustic transmission in shallow water endures severe distortion as a result of the extensive intersymbol interference and Doppler shift, caused by the time variable multipath nature of the channel. In this research a Single Input Multiple Output (SIMO) acoustic communication system is developed to improve the reliability of the high data rate communications at short range in the shallow water acoustic channel. The proposed SIMO communication system operates at very high frequency and combines spatial diversity and decision feedback equalizer in a multilevel adaptive configuration. The first configuration performs selective combining on the equalized signals from multiple receivers and generates quality feedback parameter for the next level of combining. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2015. / FAU Electronic Theses and Dissertations Collection

Cache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the success of real-time embedded systems. Various cache optimization schemes have been proposed to address the performance, power consumption, and predictability issues. However, currently available solutions are not adequate for real-time embedded systems as they do not address the performance, power consumption, and execution time predictability issues at the same time. Moreover, existing solutions are not suitable for dealing with multi-core architecture issues. In this dissertation, we develop a methodology through cache optimization for real-time embedded systems that can be used to analyze and improve execution time predictability and performance/power ratio at the same time. This methodology is effective for both single-core and multi-core systems. First, we develop a cache modeling and optimization technique for single-core systems to improve performance. Then, we develop a cache modeling and optimization technique for multi-core systems to improve performance/power ratio. We develop a cache locking scheme to improve execution time predictability for real-time systems. We introduce Miss Table (MT) based cache locking scheme with victim cache (VC) to improve predictability and performance/power ratio. MT holds information about memory blocks, which may cause more misses if not locked, to improve cache locking performance. / VC temporarily stores the victim blocks from level-1 cache to improve cache hits. In addition, MT is used to improve cache replacement performance and VC is used to improve cache hits by supporting stream buffering. We also develop strategies to generate realistic workload by characterizing applications to simulate cache optimization and cache locking schemes. Popular MPEG4, H.264/AVC, FFT, MI, and DFT applications are used to run the simulation programs. Simulation results show that newly introduced Miss Table based cache locking scheme with victim cache significantly improves the predictability and performance/power ratio. In this work, a reduction of 33% in mean delay per task and a reduction of 41% in total power consumption are achieved by using MT and VCs while locking 25% of level-2 cache size in an 4-core system. It is also observed that execution time predictability can be improved by avoiding more than 50% cache misses while locking one-fourth of the cache size. / by Abu Asaduzzaman. / Vita. / Thesis (Ph.D.)--Florida Atlantic University, 2009. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2009. Mode of access: World Wide Web.

Includes bibliographical references (leaves 189-191). / Thesis (S.M. in Oceanographic Engineering)--Joint Program in Oceanography/Applied Ocean Science and Engineering (Massachusetts Institute of Technology, Dept. of Mechanical Engineering; and the Woods Hole Oceanographic Institution), 2006. / (cont.) To that end, the space-time correlations of the error, turbulence, and wave processes are developed and then utilized to find the extent to which the environmental and internal processing parameters contribute to this error. It is found that the wave-induced velocities, even when filtered, introduce error variances which are of similar magnitude to that of the Reynolds stresses. / The challenge of estimating the Reynolds stress in an energetic ocean environment derives from the turbulence process overlapping in frequency, or in wavenumber, with the wave process. It was surmised that they would not overlap in the combined wavenumber-frequency spectrum, due to each process having a different dispersion relationship. The turbulence process is thought to obey a linear dispersion relationship, as the turbulent flow is advected with the mean current (Taylor's frozen turbulence approximation). However, the Acoustic Doppler Current Profiler (ADCP) looks at radial wavenumbers and frequencies, and finds overlap. Another approach is to exploit the physical differences of each process, namely that the wave induced velocities are correlated over much larger distances than the turbulence induced velocities. This method was explored for current meters by Shaw and Trowbridge. Upon adapting the method for the ADCP, it is found that the resulting Reynolds stress estimates are of the correct order of magnitude, but somewhat noisy. The work of this thesis is to uncover the source of that noise, and to quantify the performance limits of estimating the Reynolds Stress when using ADCP measurements that are contaminated with strong wave-induced velocities. / by Mark Rapo. / S.M.in Oceanographic Engineering

Automatic speech recognition (ASR) is one of the most important research areas in the field of speech technology and research. It is also known as the recognition of speech by a machine or, by some artificial intelligence. However, in spite of focused research in this field for the past several decades, robust speech recognition with high reliability has not been achieved as it degrades in presence of speaker variabilities, channel mismatch condi- tions, and in noisy environments. The superb ability of the human auditory system has motivated researchers to include features of human perception in the speech recognition process. This dissertation investigates the roles of perceptual features of human hearing in automatic speech recognition in clean and noisy environments. Methods of simplified synaptic adaptation and two-tone suppression by companding are introduced by temporal processing of speech using a zero-crossing algorithm. It is observed that a high frequency enhancement technique such as synaptic adaptation performs better in stationary Gaussian white noise, whereas a low frequency enhancement technique such as the two-tone sup- pression performs better in non-Gaussian non-stationary noise types. The effects of static compression on ASR parametrization are investigated as observed in the psychoacoustic input/output (I/O) perception curves. A method of frequency dependent asymmetric compression technique, that is, higher compression in the higher frequency regions than the lower frequency regions, is proposed. By asymmetric compression, degradation of the spectral contrast of the low frequency formants due to the added compression is avoided. A novel feature extraction method for ASR based on the auditory processing in the cochlear nucleus is presented. The processings for synchrony detection, average discharge (mean rate) processing and the two tone suppression are segregated and processed separately at the feature extraction level according to the differential processing scheme as observed in the AVCN, PVCN and the DCN, respectively, of the cochlear nucleus. It is further observed that improved ASR performances can be achieved by separating the synchrony detection from the synaptic processing. A time-frequency perceptual spectral subtraction method based on several psychoacoustic properties of human audition is developed and evaluated by an ASR front-end. An auditory masking threshold is determined based on these psychoacoustic e?ects. It is observed that in speech recognition applications, spec- tral subtraction utilizing psychoacoustics may be used for improved performance in noisy conditions. The performance may be further improved if masking of noise by the tonal components is augmented by spectral subtraction in the masked region.

Speech recognition systems have been implemented using a wide range of signal processing techniques including neuromorphic/biological inspired and Digital Signal Processing techniques. Neuromorphic/biologically inspired techniques, such as silicon cochlea models, are based on fairly simple yet highly parallel computation and/or computational units. While the area of digital signal processing (DSP) is based on block transforms and statistical or error minimization methods. Essential to each of these techniques is the first stage of extracting meaningful information from the speech signal, which is known as feature extraction. This can be done using biologically inspired techniques such as silicon cochlea models, or techniques beginning with a model of speech production and then trying to separate the the vocal tract response from an excitation signal. Even within each of these approaches, there are multiple techniques including cepstrum filtering, which sits under the class of Homomorphic signal processing, or techniques using FFT based predictive approaches. The underlying reality is there are multiple techniques that have attacked the problem in speech recognition but the problem is still far from being solved. The techniques that have shown to have the best recognition rates involve Cepstrum Coefficients for the feature extraction and Hidden-Markov Models to perform the pattern recognition. The presented research develops an analog system based on programmable analog array technology that can perform the initial stages of auditory feature extraction and recognition before passing information to a digital signal processor. The goal being a low power system that can be fully contained on one or more integrated circuit chips. Results show that it is possible to realize advanced filtering techniques such as Cepstrum Filtering and Vector Quantization in analog circuitry. Prior to this work, previous applications of analog signal processing have focused on vision, cochlea models, anti-aliasing filters and other single component uses. Furthermore, classic designs have looked heavily at utilizing op-amps as a basic core building block for these designs. This research also shows a novel design for a Hidden Markov Model (HMM) decoder utilizing circuits that take advantage of the inherent properties of subthreshold transistors and floating-gate technology to create low-power computational blocks.

The objective of this dissertation is to investigate the performance of the recently proposed MIMO technology in real indoor environments based on channel measurements centered at 5.8 GHz. First, a MIMO channel measurement system is implemented based on the virtual antenna array infrastructure. This measurement testbed can acquire the wideband channel matrices of MIMO systems with arbitrary array geometries. The measurement system structure and measurement procedure are described in detail in the first part. The second part is about MIMO channel modeling. Two novel number-of-sources detection algorithms, which are more robust and suitable for practical applications than traditional methods, are proposed. The MIMO path parameters, including delay, DOA, and DOD are estimated from measured data by several estimation schemes based on the ESPRIT algorithm. The accuracies of these estimation schemes are evaluated in terms of the estimation error between the capacities of the directly measured and the reconstructed channels. Moreover, based on ray tracing and measurement results, the spherical wave model is suggested to replace conventional plane wave model in order to prevent the capacity underestimation of short-range MIMO channels. An important observation is that short-range MIMO can achieve full capacity in free space channel. A threshold distance is derived to determine whether the spherical wave model is necessary. In the final part, measurements conducted in the Residential Laboratory are used to investigate the impact of element spacing, LOS, interference, spatial correlation between the interfering and data links, and stream control. A capacity enhancement scheme, which improves the performance by adapting the element locations, is implemented using our measurement system. Finally, the performances of beam selection and antenna selection in combination with MIMO technologies are compared in both narrowband and wideband channels.

With the development of VLSI and wireless communication technology, portable devices such as personal digital assistants (PDAs), pocket PCs, and mobile phones have gained a lot of popularity. Many such devices incorporate a speech recognition engine, enabling users to interact with the devices using voice-driven commands and text-to-speech synthesis. The power consumption of DSP microprocessors has been consistently decreasing by half about every 18 months, following Gene's law. The capacity of signal processing, however, is still significantly constrained by the limited power budget of these portable devices. In addition, analog-to-digital (A/D) converters can also limit the signal processing of portable devices. Many systems require very high-resolution and high-performance A/D converters, which often consume a large fraction of the limited power budget of portable devices. The proposed research develops a low-power audio signal enhancement system that combines programmable analog signal processing and traditional digital signal processing. By utilizing analog signal processing based on floating-gate transistor technology, the power consumption of the overall system as well as the complexity of the A/D converters can be reduced significantly. The system can be used as a front end of portable devices in which enhancement of audio signal quality plays a critical role in automatic speech recognition systems on portable devices. The proposed system performs background audio noise suppression in a continuous-time domain using analog computing elements and acoustic echo cancellation in a discrete-time domain using an FPGA.

When computational resources are limited, especially multipliers, distributed arithmetic (DA) is used in lieu of the typical multiplier-based filtering structures. However, DA is not well suited for adaptive applications. The bottleneck is updating the memory table. Several attempts have been done to accelerate updating the memory, but at the expense of additional memory usage and of convergence speed. To develop an adaptive DA filter with an uncompromised convergence rate, the memory table must be fully updated. In this research, an efficient method for fully updating a DA memory table is proposed. The proposed update method is based on exploiting the temporal locality of the stored data and subexpression sharing. The proposed update method reduces the computational workload and requires no additional memory resources. DA using the proposed update method is called conjugate distributed arithmetic. Filters can also be constructed from analog components. Often, for lower precision computations, analog circuits use less power and less chip area than their digital counterparts. However, digital components are often used because of their ease of reprogrammability. Achieving such reprogrammability in analog is possible, but at the expense of additional chip area. A reprogrammable mixed-signal DA finite impulse response (FIR) filter is proposed to address the issues with reprogrammable analog FIR filters that are constructing compact reprogrammable filtering structures, non-symmetric and imprecise filter coefficients, inconsistent sampling of the input data, and input sample data corruption. These issues are successfully addressed using distributed arithmetic, digital registers, and epots. Also, a mixed-signal DA second-order section (SOS), which is used as the building block for higher order infinite impulse response filters, was proposed. The type of issues with an analog SOS filter are similar to those of an analog FIR filter, which are the lack of a compact reprogrammable filtering structure, the imprecise filter coefficients, the inconsistent sampling of the data, and the corruption of the data samples. These issues are successfully addressed using distributed arithmetic and digital registers.