Thesis (doctoral)--Helsinki University of Technology, 2007. / Includes bibliographical references. Also available on the World Wide Web.

Thesis (doctoral)--Helsinki University of Technology, 2006. / Includes bibliographical references. Also available on the World Wide Web.

No description available.

A novel structure related to Seperation by Implanted Oxygen (SIMOX) of NiSi2/SiO2/Si is studied for two primary reasons: the importance of metal silicide and insulating oxide in IC devices and the difficulty of direct growth of crystalline silicide on amorphous substrates.

Microelectronics has enjoyed great success in the past century. As the technology node progresses, the complementary metal-oxide-semiconductor scaling has already reached a wall, and serious challenges in high-bandwidth interconnects and fast-speed signal processing arise. The incorporation of photonics to microelectronics provides potential solutions. The theme of this thesis is focused on the novel applications of travelling-wave microresonators such as microdisks and microrings for the on-chip optical interconnects and signal processing. Challenges arising from these applications including theoretical and experimental ones are addressed. On the theoretical aspect, a modified version of coupled mode theory is offered for the TM-polarization in high index contrast material systems. Through numerical comparisons, it is shown that our modified coupled mode theory is more accurate than all the existing ones. The coupling-induced phase responses are also studied, which is of critical importance to coupled-resonator structures. Different coupling structures are studied by a customized numerical code, revealing that the phase response of symmetric couplers with the symmetry about the wave propagating direction can be simply estimated while the one of asymmetric couplers is more complicated. Mode splitting and scattering loss, which are two important features commonly observed in the spectrum of high-Q microresonators, are also investigated. Our review of the existing analytical approaches shows that they have only achieved partial success. Especially, different models have been proposed for several distinct regimes and cannot be reconciled. In this thesis, a unified approach is developed for the general case to achieve a complete understanding of these two effects. On the experimental aspect, we first develop a new fabrication recipe with a focus on the accurate dimensional control and low-loss performance. HSQ is employed as the electron-beam resist, and the lithography and plasma etching steps are both optimized to achieve vertical and smooth sidewalls. A third-order temperature-insensitive coupled-resonator filter is designed and demonstrated in the silicon-on-insulator (SOI) platform, which serves as a critical building block element in terabit/s on-chip networks. Two design challenges, i.e., a broadband flat-band response and a temperature-insensitive design, are coherently addressed by employing the redundant bandwidth of the filter channel caused by the dispersion as thermal guard band. As a result, the filter can accommodate 21 WDM channels with a data rate up to 100 gigabit/s per wavelength channel, while providing a sufficient thermal guard band to tolerate more than ±15°C temperature fluctuations in the on-chip environment. In this thesis, high-Q microdisk resonators are also proposed to be used as low-loss delay lines for narrowband filters. Pulley coupling scheme is used to selectively couple to one of the radial modes of the microdisk and also to achieve a strong coupling. A first-order tunable narrowband filter based on the microdisk-based delay line is experimentally demonstrated in an SOI platform, which shows a tunable bandwidth from 4.1 GHz to 0.47 GHz with an overall size of 0.05 mm². Finally, to address the challenges for the resonator-based delay lines encountered in the SOI platform, we propose to vertically integrate silicon nitride to the SOI platform, which can potentially have significantly lower propagation loss and higher power handling capability. High-Q silicon nitride microresonators are demonstrated; especially, microresonators with a 16 million intrinsic Q and a moderate size of 240 µm radius are realized, which is one order of magnitude improvement compared to what can be achieved in the SOI platform using the same fabrication technology. We have also successfully grown silicon nitride on top of SOI and a good coupling has been achieved between the silicon nitride and the silicon layers.

Master of Science / Department of Electrical and Computer Engineering / William Kuhn / Studies of Silicon-on-Sapphire (SOS) CMOS device operation in cryogenic environments are presented. The main focus was to observe the characteristic changes in high, medium and low threshold SOS NFETs as well as SOS silicide blocked (SN) resistors when the operational temperature is in the devices’ freeze-out range below 77 Kelvin. The measurements taken will be useful to any integrated circuit (IC) designer creating devices based on an SOS process intended to operate in cryogenic environments such as superconducting electronics and planetary probes. First, a 1N4001 rectifier and a 2N7000 NFET were tested to see how freeze-out effects standard diode and MOS devices. These devices were tested to see if the measurement setup could induce carrier freeze-out. Next, SOS devices were studied. Data was collected at room temperature and as low as 5 Kelvin to observe resistance changes in an SN resistor and kink effect, threshold voltage shifts and current level changes in transistors. A 2μm high threshold NFET was tested at room temperature, 50 Kelvin, 30 Kelvin and 5 Kelvin to observe effects on I-V curves at different temperatures with-in the freeze-out range. A 2μm medium threshold NFET was tested down to 56 Kelvin to see if the behavior is similar to the high threshold FET. A 2μm intrinsic, or low threshold, NFET was also tested with the assumption it would be the most susceptible to carrier freeze-out. All of the devices were found to behave well with only mild effects noted.

No description available.

An apodized grating coupler with the best coupling efficiency hitherto reported for shallow-etched waveguide grating couplers is described. By appropriate choice of waveguide/grating thicknesses and varying the coupling strength of the grating coupler via tailoring its fill factor to optimize the mode matching, a coupling loss of only 1.2dB was obtained for each fiber/silicon waveguide interface with a slightly titled optical fiber. / Photonic integrated circuits (PICs) based on Silicon-on-insulator (SOI) substrate were proposed to make miniaturized photonic devices on chip, so that low-cost and compact devices for applications including sensing, inter/intra-chip communications and optical fiber communications could be made. One of the key challenges in the development of highly integrated PICs is efficient coupling of light between a submicron-sized nanophotonic wire and an optical fiber due to the large loss inherent from the mismatch in mode field size between the optical fibers and the nanophotonic wire waveguides. An attractive approach for efficient coupling is to use diffractive grating couplers which show many advantages over alternative approaches. However the angled alignment of the optical fiber to the grating as reported in the previous work is not desirable for a low-cost optical packaging process. / The 2D grating couplers could be used as polarization splitter. Polarization insensitive coupling and polarization-diversity circuits are realized by the 2D grating couplers. We also demonstrated a novel silicon waveguide grating which serves dual functions: as a 1x2 variable integrated beam splitter/combiner and as an out-of plane diffractive element for coupling light. The split ratio can be tuned by changing the launch position of the optical fiber without introducing much excess loss. An integrated Mach-Zehnder interferometer (MZI) is implemented with this novel functional element. This MZI was demonstrated as a demodulator for differential phase-shift-keying (DPSK) signal. / We demonstrated a simple technique to realize vertical fiber coupling with linearly chirped grating periods. No additional fabrication process is required yet a comparable coupling efficiency is achieved with the proposed chirped grating couplers with vertical optical fibers. Design and experimental results of onedimensional (lD) gratings, two-dimensional (2D) gratings, focusing gratings and fully-etched nanoholes gratings are described in the thesis. We also describe the waveguides and grating couplers fabricated on silicon-on-sapphire for mid-infrared applications. / Chen, Xia. / Adviser: H.K. Tsang. / Source: Dissertation Abstracts International, Volume: 73-03, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Chan Po Shan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 79). / Text in English; abstracts in English and Chinese. / Chan Po Shan. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Application of Optical Waveguides --- p.1 / Chapter 1.2 --- Planar Waveguide Characterizations --- p.2 / Chapter 1.3 --- Silicon-On-Insulator Rib Waveguides --- p.3 / Chapter 1.4 --- Polarization compensation schemes --- p.4 / Chapter 1.5 --- Objectives --- p.6 / Chapter 2 --- Silicon-On-Insuiator Rib Waveguides --- p.9 / Chapter 2.1 --- Properties of Silicon Waveguides --- p.9 / Chapter 2.2 --- Single Mode Rib Waveguides Simulations --- p.11 / Chapter 2.3 --- Special design optimisations --- p.14 / Chapter 2.4 --- Fabrications and Results --- p.16 / Chapter 3 --- Polarization Characteristics of SOI Rib Waveguides --- p.20 / Chapter 3.1 --- Properties of silicon and effect of rib structure --- p.20 / Chapter 3.2 --- Polarization affected by Form Birefringence --- p.21 / Chapter 3.3 --- Case Study: Arrayed Waveguide Grating --- p.23 / Chapter 3.4 --- Possibility of polarization Compensation in planar waveguides --- p.26 / Chapter 4 --- Fixed Polarization Compensation Techniques --- p.30 / Chapter 4.1 --- Theoretical analysis of slant rib waveguides on polarization --- p.30 / Chapter 4.2 --- Focused Ion Beam Trimming of SOI waveguides --- p.31 / Chapter 4.3 --- Possible applications --- p.36 / Chapter 5 --- Tuneable Polarization Compensation Techniques --- p.41 / Chapter 5.1 --- stress on rib waveguide for polarization compensation --- p.41 / Chapter 5.2 --- Magnetostriction and Magnetostrictive Materials --- p.42 / Chapter 5.3 --- Sputtering of soft magnetic layer on SOI rib waveguides --- p.46 / Chapter 5.4 --- Test results and Analysis --- p.47 / Chapter 6 --- Advanced SOI Devices --- p.55 / Chapter 6.1 --- Unique planar optoelectronics devices --- p.55 / Chapter 6.2 --- Simulation and Fabrications --- p.57 / Chapter 6.3 --- Test Results and Discussion --- p.58 / Chapter 7 --- Conclusion --- p.62 / Chapter 7.1 --- Summary --- p.62 / Chapter 7.2 --- Future work --- p.63 / Appendices / Chapter A1 --- Effective Index Method --- p.66 / Chapter A2 --- Beam Propagation Method --- p.70 / Chapter A3 --- SOI Rib Waveguide Fabrication --- p.72 / Chapter A4 --- Focused Ion Beam --- p.74 / Chapter A5 --- Polarization Optics --- p.76 / List of Publications --- p.79

A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption. The targeted applications in mind for the ADCs are read channel and ultra wideband radio applications. These applications requires a resolution of at least four to six bits and a sampling frequency of above 1 GHz. Hence the flash ADC topology is chosen for the implementations. In this work we do also propose enhancements to the flash ADC converter. Further, this work also investigates introduction of dynamic element matching (DEM) into a flash ADC. A method to introduce DEM into the reference net of a flash ADC is proposed and evaluated. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a top-down design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level using MATLAB and SpectreHDL. The modeling results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC implementation has a conventional topology. It has a resistor net connected to a number of latched comparators and employs a ones-counter thermometer-to-binary decoder. This ADC serves as a reference for evaluating the other topologies. The measurements indicate a maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an SFDR of about 29 to 35 dB. The second ADC has a similar topology as the reference ADC, but its thermometer-to-binary decoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact decoder with a regular structure and a short critical path. The measurements show that it is more efficient in terms of power consumption than the ones-counter decoder and it has 40 % smaller chip area. Further, the SNDR and SFDR are similar as for the reference ADC, but its maximum sampling frequency is about 660 MHz. The third ADC demonstrates the introduction of DEM into the reference net of a flash ADC. Our proposed technique requires fewer switches in the reference net than other proposals. Our technique should thereby be able to operate at higher sampling and input frequencies than compared with the other proposals. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB in average when introducing DEM. The transistor level simulations in Cadence and measurements of the ADC with DEM indicates that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying DEM. The smaller improvement indicated by the measurements is believed to be due to a design flaw discovered during the measurements. A mask layer for the resistors of the reference net is missing, which affects their accuracy and degrades the ADC performance. The same reference net is used in the other ADCs, and therefore degrades their performance as well. Hence the measured performance is significantly lower than indicated by the transistor level simulations. Further, it is observed that the improved SFDR is traded for an increased chip area and a reduction of the maximum sampling frequency. The DEM circuitry impose a 30 % larger chip area.