High dielectric constant barium doped titanium silicon oxide films with equivalent oxide thickness below 1 nm can be prepared by liquid phase deposition. We learn from this research that the deposition rate of titanium silicon oxide films can be much enhanced by nitric acid incorporation, and the dielectric constant of materials can be increased by the dipole polarization from barium. The key parameter for the deposition rate, refractive index, and the dielectric constant of barium doped titanium silicon oxide is the molarity of barium nitrate. The electrical properties can be improved effectively by thermal annealing treatments. The optimum equivalent oxide thickness of barium doped titanium silicon oxide thin film is 0.9 nm with the optical thickness of 7.4 nm. The high dielectric constant can reach 31.9 and the leakage current density is 5 ¡Ñ 10-6 A/cm2 at the electrical field intensity of 5 MV/cm, which has high potential application for the next generation MOSFET.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 147-155). Available also in a digital version from Dissertation Abstracts.

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We have developed continuous random network (CRN) model based Metropolis Monte Carlo simulation tools which are capable of predicting the structural properties of amorphous semiconductor and oxide materials as well as their interface. To bolster the reliability of the CRN model, we have developed force fields based on gradient corrected density functional theory (DFT) calculations. Our in-house CRN-MMC tools have been massively parallelized, which allows us to create fairly large model structures within a reasonable computational time. Using the integrated CRN-MMC tools, we have elucidated the complex growth and structure of self-interstitial and vacancy clusters in silicon and the effect of strain on the structure and stability of the defect clusters. Our work for vacancy clusters suggests that small vacancy defects exclusively favor fourfold-coordination thermodynamically with no significant kinetic limitation rather than void-like structure formation, which has widely been adapted to explain the behavior and properties of vacancy defects. Our results also highlight the identification of stable high-symmetry fourfold-coordinated V₁₂ and V₃₂ clusters that could be expected to exist to a large extent in a vacancy rich region although its direct characterization appears impractical at present. Our work for self-interstitial clusters provides the first theoretical support for earlier experiments which suggest a shape transition from compact to elongated structures around n = 10. When the cluster size is smaller than 10, the stable I₄ and I₈ compact clusters are found to inhibit the formation of elongated defects, whereas the newly discovered fourfold-coordinated I₁₂ state is found to serve as an effective nucleation center for large extended defects. Our CRN-MMC approach also enabled us to elucidate the underlying mechanisms of synthesis and manipulation of Si rich insulators as well as the fundamental understanding of the relationship between the atomic structure and properties. We developed a valence force field based on a modified Keating model for the structure and energetics of amorphous Si rich oxide materials. In particular, our work emphasizes the importance of correctly describing the wide Si-O-Si angle distribution. Our work also suggests that the relative rigidity between Si and SiO₂ matrices is critical in determination of the Si/SiO₂ interface structure. The present potential model coupled with the CRN-MMC method can be used to create structural models (free of coordination defects) for complex a-SiO[subscript x]-based materials, which will further allow thorough studies of the properties of these materials. / text

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

In decades, the tremendous development of integrated circuits industry could be mostly attributed to SiO2, since its satisfactory properties as a gate dielectric candidate. The effectivity of SiO2 has been challenged since dielectric layer was scaled down below 3nm, when the gate leakage current of SiO2 became unacceptable. Institution to silicon-based CMOS techniques were proposed, but they have their own limitations. Nowadays, materials with high dielectric constants are mainstream gate dielectric materials in industry, but a SiO2 interfacial layer is still necessary to avoid gap between gate dielectric layer and Si substrate, and to minimize interface trap charges. In this thesis work, by applying lateral heating process on Si wafer with thermally grown ultrathin SiO2, the gate leakage current density could be reduced by 3-5 order of magnitude. MOS capacitors were fabricated, and electrical properties were tested with semiconductor parameter analyzer and LCR meter. The underlying mechanism of this appealing phenomenon was explored. Since unacceptable gate leakage current is one of the main reasons which prevent the scaling trend in semiconductor industry, this technology brings a possibility to post-pone the end of scaling trend, and pave a way for extensive application in industry. A new method for fabrication of MOS capacitors metal gate has been developed, and lift-off process has been replaced by wet etching process. This method provides better contact between dielectric layer and metal gate, meanwhile much easier operation.

Thesis (Ph. D.)--University of Hong Kong, 1990.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 82-92). Also available in electronic format on the Internet.