The traditional displayer ¡V CRT has already been substituted by liquid crystal displayer (LCD).The a-Si TFT is used to be a switch, while the size of the displayer increases, the require of the performance and quality of TFTs is more and more better. Therefore, it is very important subject to study the stability and to improve the performance of a-Si TFTs. In this thesis, we fabricate another new structure (asymmetry dual-gate TFTs).For asymmetry dual-gate TFTs, the ITO back gate is extended to the middle of the channel and only covered on the drain contact. The new structure has the advantages of dual-gate TFTs. With dual-channel conduction, it exhibit higher Ion and lower photo leakage current performance than the conventional inverted staggered TFTs. In addition, we use the asymmetry dual-gate structure to investigate how the parasitic capacitance influences the feed-through voltage by C-V measurement. We also to investigate the influences of electrical characteristics with the ITO back gate whether or not overlap the source contact. The asymmetry in on current with source-drain swapping can be attributed to the difference in the ITO back gate whether overlaps the source contact. Finally, it simulated the process of the degradation on the TFTs to find the stability mechanism of the TFTs.

The cost of photovoltaic electricity needs to be significantly reduced in order to achieve a high electricity market penetration. Thin-film solar cells have good potential to achieve such cost savings though (i) large-area deposition onto low-cost foreign substrates, (ii) more streamlined processing, (iii) monolithic cell interconnection, and very efficient use of the expensive semiconductor material. Polycrystalline silicon (poly-Si) on glass is a promising technology for the cost-effective large volume production of PV modules since it (i) makes use of an abundant raw material, (ii) is non-toxic, (iii) does not suffer from light-induced degradation, and (iv) does not rely on TCO layers. Usually plasma enhanced chemical vapour deposition (PECVD) is used for the layer formation. This thesis explores the use of e-beam evaporation as deposition method since it is potentially much faster and cheaper than PECVD. The resulting solar cells are referred to as EVA (from EVAporation). Two inherent shunting mechanisms in EVA cells are demonstrated to be shunting through sub-micron sized pinholes when the back electrode is deposited and shunting between the emitter and the absorber layer at the glass-side electrode. Through the improved understanding of these shunting mechanisms it was possible to develop a suitable metallisation scheme for EVA cells using an aligned deposition of emitter and back surface field line contacts and a specially developed shunt mitigation etching technique. For the first time appreciable efficiencies of up to 5.2% were demonstrated on this material. It was also shown that only very lightly doped absorber layers can lead to the required high short-circuit currents in EVA cells. The resulting cells are currently completely limited by space charge region recombination occurring with comparatively low ideality factors of only ~ 1.4 This thesis also demonstrates the usefulness of Jsc-Suns measurements and investigates optical loss mechanisms in the current devices. Advanced modelling of distributed series resistance effects, influencing Suns-Voc, m-Voc and Jsc-Suns curves, is employed. PC1D modelling is used to extract relevant device parameters. In this work it was found that the diffusion length in the best EVA cells is longer than the absorber layer and that insufficient light trapping is currently the major hurdle to higher cell efficiencies. From the obtained results it can be concluded that EVA solar cells are promising candidates for the low-cost and high-volume production of solar modules.

The cost of photovoltaic electricity needs to be significantly reduced in order to achieve a high electricity market penetration. Thin-film solar cells have good potential to achieve such cost savings though (i) large-area deposition onto low-cost foreign substrates, (ii) more streamlined processing, (iii) monolithic cell interconnection, and very efficient use of the expensive semiconductor material. Polycrystalline silicon (poly-Si) on glass is a promising technology for the cost-effective large volume production of PV modules since it (i) makes use of an abundant raw material, (ii) is non-toxic, (iii) does not suffer from light-induced degradation, and (iv) does not rely on TCO layers. Usually plasma enhanced chemical vapour deposition (PECVD) is used for the layer formation. This thesis explores the use of e-beam evaporation as deposition method since it is potentially much faster and cheaper than PECVD. The resulting solar cells are referred to as EVA (from EVAporation). Two inherent shunting mechanisms in EVA cells are demonstrated to be shunting through sub-micron sized pinholes when the back electrode is deposited and shunting between the emitter and the absorber layer at the glass-side electrode. Through the improved understanding of these shunting mechanisms it was possible to develop a suitable metallisation scheme for EVA cells using an aligned deposition of emitter and back surface field line contacts and a specially developed shunt mitigation etching technique. For the first time appreciable efficiencies of up to 5.2% were demonstrated on this material. It was also shown that only very lightly doped absorber layers can lead to the required high short-circuit currents in EVA cells. The resulting cells are currently completely limited by space charge region recombination occurring with comparatively low ideality factors of only ~ 1.4 This thesis also demonstrates the usefulness of Jsc-Suns measurements and investigates optical loss mechanisms in the current devices. Advanced modelling of distributed series resistance effects, influencing Suns-Voc, m-Voc and Jsc-Suns curves, is employed. PC1D modelling is used to extract relevant device parameters. In this work it was found that the diffusion length in the best EVA cells is longer than the absorber layer and that insufficient light trapping is currently the major hurdle to higher cell efficiencies. From the obtained results it can be concluded that EVA solar cells are promising candidates for the low-cost and high-volume production of solar modules.

In this dissertation, the electrical characteristics of generally used hydrogenated amorphous silicon (a-Si:H) TFTs in LCD and newly risen amorphous indium-gallium-zinc oxide (a-IGZO) TFTs were studied. For modern mobile display and large-size flat panel display application, the traditional thin-film transistor-liquid crystal display (TFT-LCD) technology confronts with a lot of challenges and problems. In general, flexible displays must exhibit some bending ability; however, bending applies mechanical strain to electronic circuits and affects device characteristics. Therefore, the electrical characteristics of a-Si:H TFTs fabricated on stainless steel foil substrates with uniaxial bending were investigated at different temperatures. Experimental results showed that the on-state current and threshold voltage degraded under outward bending. This is because outward bending will induce the increase of band tail states, affecting the transport mechanism at different temperatures. In addition, for practical operation, the electrical characteristics of a-Si:H TFTs under flat and bending situations after AC/DC stress at different temperatures were studied. It was found that high temperature and mechanical bending played important roles under AC stress. The dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress was also observed. Because a-Si:H is a photosensitive material, the high intensity backlight illumination will degrade the performance of a-Si:H TFTs. Thus, the photo-leakage current of a-Si:H TFTs under illumination was investigated at different temperatures. Experimental results showed that a-Si:H TFTs exhibited a pool performance at lower temperatures. The indirect recombination rate and the parasitic resistance (Rp) are responsible for the different photo-leakage-current trends of a-Si:H TFTs under varied temperature operations. To investigate the photo-leakage current, the a-Si:H TFTs were exposed to ultraviolet (UV) light irradiation. It was found that the photo current of a-Si:H TFTs was reduced after UV light irradiation. The detail mechanisms on reducing/increasing photo-leakage current by UV light irradiation were discussed. Recently, the oxide-based semiconductor TFT, especially a-IGZO TFT, is considered as one of promising candidates for active matrix flat-panel display. However, the a-IGZO TFT exists significant electrical instability issue and manufacturing problems. As a consequence, we investigated the effect of hydrogen incorporation on a-IGZO TFTs to reduce interface states between active layer and insulator. Experimental results showed that the electrical characteristics of hydrogen-incorporated a-IGZO TFTs were improved. The threshold voltage shift (£GVth) in hysteresis loop is suppressed from 4 V to 2 V due to the hydrogen-induced passivation of the interface trap states. Finally, we reported the effect of ambient environment on a-IGZO TFT instability. As a-IGZO TFTs were stored in atmosphere environment for 40 days, the transfer characteristics accompanying strange hump were observed during bias-stress. The hump phenomenon is attributed to the absorption of H2O molecule. Additionally, the sufficient electric field is also necessary to cause this anomalous transfer characteristic.

In this dissertation, we investigates the electrical stress induced degradation in low-temperature polycrystalline-silicon thin film transistors (LTPS TFTs) applied for system-on-panel (SOP), including the electrical degradations of device for switch operation in active matrix flat-panel displays, driving circuit and nonvolatile memory. Finally, we also present the reliability of LTPS TFTs applied for flexible displays. In first part, electrical degradation of conventional and pattered metal-shielding LTPS TFTs under darkened and illuminated dynamic AC stresses are investigated. Experimental results reveal that competitive mechanisms are generated in conventional LTPS TFTs during illuminated stress, namely, carrier increase and electric field weakening. This phenomenon is verified by stressing the patterned source/drain open metal-shielding LTPS TFTs, which determines that the electric field weakening dominates; conversely, the carrier increase is dominated the electrical degradation in channel open metal-shielding device under illuminated stress. In addition, an improvement in anomalous on-current and subthreshold swing (S.S.) in n-channel LTPS TFTs after positive gate bias stress are studied. These improved electric properties are due to the hole trapping at SiO2 above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the S.S.. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. Secondly, a mechanism of anomalous capacitance in p-channel LTPS TFTs was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. Besides, by fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and Thermal-Field emission. In addition, the charge density calculated from the Cch-Vg measurement also the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain. In third part, in order to realize the reliability in p-channel TFTs under illuminated environment operation, the degradation of negative bias temperature instability (NBTI) with illumination effect is investigated. The generations of interface state density (Nit) are identical under various illuminated intensity DC NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap) under illumination was more significant than for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased Ntrap degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region that from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase of Ntrap degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in poly-Si bulk, affecting photosensitivity in LTPS TFTs. Besides, the transient effect assisted NBTI degradation in p-channel LTPS TFTs under dynamic stress is also presented, in which the degradation of the Ntrap becomes more significant as rise time decreases to 1 £gs. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant Ntrap increase is assisted by this transient effect. Fourthly, we study the electric properties of n- and p-channel LTPS TFTs under the mechanical tensile strain. The improved on-current for tensile strained n-channel TFTs is originated form an increase in energy difference between 2- and 4-fold valleys, reducing the inter-valley scattering and further improving the carrier mobility. On the contrary, the hole mobility decreases in p-channel, suggesting the split between the light hole and heavy hole energy bands and an increase in hole population on the heavy hole energy band of poly-Si when the uniaxial tensile strain is parallel to the channel direction. In addition, the Nit and Ntrap degradations induced by NBTI for tensile strained LTPS TFTs are more pronounced than in the unstrained. Extracted density-of-states (DOS) and conduction activation energy (EA) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during the NBTI stress. Therefore, the NBTI degradation is more significant after tensile strain than in an unstrained condition. Finally, the SONOS-TFT applied to nonvolatile memory is prepared and studied. In the gate disturb stress, a parasitic capacitance and resistance in off-state region are identified as electrons trapped in the gate-insulator (GI) near the defined gate region. Meanwhile, these trapping electrons induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

L'objectif de cette thèse est de contribuer à la compréhension des propriétés optoélectroniques des couches minces de silicium hydrogénée, une étude détaillée a été effectuée. Les échantillons ont été déposés par 13,56 MHz PECVD (Plasma Enhanced Chemical Vapor Deposition) à partir du silane dilué avec l'argon (96 %). La température du substrat a été fixée à 200 °C. L'influence des paramètres de dépôts sur les propriétés optiques des échantillons a été étudiée par spectroscopie UV -Vis -NIR. L'évolution structurelle a été étudiée par spectroscopie Raman, TEM, AFM, FTIR et par diffraction des rayons X (XRD). La déposition des couches intrinsèques a été faite dans cette étude dans le but d'obtenir la transition de l'état amorphe à la phase cristalline des matériaux. La pression de dépôt varie de 400 mTorr à 1400 mTorr et la puissance de 50 à 250 W. La caractérisation structurelle montre qu'au-delà de 160 W, nous avons observé une transition amorphe nanocristalline, avec une augmentation de la fraction cristalline en augmentant la puissance et la pression. Les couches sont déposées avec des vitesses de dépôt relativement élevées (3.5 - 8 Å/s), ce qui est très souhaitable pour la fabrication des cellules photovoltaïques. La vitesse de dépôt augmente avec l'augmentation de la puissance et de la pression. Des différentes fractions cristallines et tailles des cristallites ont été obtenues en contrôlant la pression et la puissance. Ces modifications de structure ont été corrélées avec la variation des propriétés optiques et électriques des couches minces déposées. / The main objective of this thesis is to contribute to the understanding of the optoelectronics properties of hydrogenated nanocrystalline silicon thin films, a detailed study has been conducted. The samples were deposited by 13.56 MHz PECVD (Plasma Enhanced Chemical Vapor Deposition) of silane argon mixture. The argon dilution of silane for all samples studied was 96% by volume. The substrate temperature was fixed at 200 °C. The influence of depositions parameters on optical proprieties of samples was studied by UV-Vis-NIR spectroscopy. The structural evolution was studied by Raman spectroscopy, TEM, AFM, FTIR and X-ray diffraction (XRD). Intrinsic-layer samples depositions were made in this experiment in order to obtain the transition from the amorphous to crystalline phase materials. The deposition pressure varied from 400 mTorr to 1400 mTorr and the RF power from 50 to 250 W. The structural evolution studies show that beyond 160 W, we observed an amorphous-nanocrystalline transition, with an increase in crystalline fraction by increasing RF power and working pressure. Films near the amorphous to nanocrystalline transition region are grown at reasonably high deposition rates (3.5- 8 Å/s), which are highly desirable for the fabrication of cost effective devices. The deposition rate increases with increasing RF power and process pressure. Different crystalline fractions and crystallite size can be achieved by controlling the process pressure and RF power. These structural changes are well correlated to the variation of optical and electrical proprieties of the thin films.

In order to meet the requests of the application as pixel switch and current driver in next generation active-matrix liquid crystal displays (AMLCD) and active-matrix organic light-emitting diodes (AMOLED). The materials of low temperature poly-silicon (LTPS) and metal-oxide are supposed to be the most potential material for active layer of thin-film transistors (TFTs) due to their high mobility compared to the traditional amorphous silicon TFTs. Therefore, in order to make the LTPS TFTs and metal-oxide TFTs affordable for the practical applications, the understanding of instability and reliability is critically important. In the first part, we studied the nonvolatile memory characteristics of polycrystalline-silicon thin-film-transistors (poly-Si TFTs) with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant gate induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection method to counteract programmed electrons and this method can exhibit good sustainability because the injected hot holes can remain in the nitride layer after repeated operations. On the other hand, we also investigated the degradation behavior of SONOS-TFT under off-state stress. After the electrical stress, the significant on-state degradation indicates that the interface states accompanied with hot-hole injection. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Furthermore, we also performed the identical off-state stress for the device with different memory states. The different degradation behavior under different memory states is attributed to the different overlap region of injected holes and trap states. In the second part, the degradation mechanism of indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs) caused by gate-bias stress performed in the dark and light illumination was investigated. The parallel threshold voltage indicates that charge trapping model dominates the degradation behavior under positive gate-bias stress. However, the degradation of negative gate bias stress is much slighter than the positive gate bias stress since the IGZO material is hard to induced hole inversion layer. In addition, the hole mobility is much lower than electron resulting in ignorable hole trapping effect. On the other hand, the identical positive and negative gate bias stress performed under light illumination exhibit opposite degradation behavior compared with dark stress. This degradation variation under dark and light illumination can be attributed to the effectively energy barrier variation of electron and hole trapping. Furthermore, to further investigate the light induced instability for IGZO TFTs, the device with and without a SiOx passivation were investigated under light illumination. The experiment results indicate that oxygen adsorption and desorption dominate the light induced instability for unpassivated device and the trap states caused during the passivation layer deposition process will induce apparent subthreshold photo-leakage current under light illumination. In the third part, we investigated the degradation mechanism of IGZO TFTs under hot-carrier and self-heating stress. Under hot-carrier stress, except the electron trapping induced positive Vt shift, an apparent on-current degradation behavior indicates that trap states creation. On the other hand, the identical hot-carrier stress performed in the asymmetric source/drain structure exhibits different degradation behavior compared with symmetric source/drain structure. For asymmetric structure, the strong electrical field in the I-shaped drain electrode will induce channel hot electron injection near the drain side and cause asymmetric threshold voltage degradation. In this part we also investigated the degradation behavior under self-heating stress. The apparent positive threshold voltage (Vt) shift and on-current degradation indicate that the combination of trap states generation and electron trapping effect occur during stress. The trap states generation is caused by the combination of Joule heating and the large vertical field. Moreover, the Joule heating generated by self-heating operation can enhance electron trapping effect and cause larger Vt shift in comparison with the gate-bias stress. Finally, the electrical properties and photo sensitivity of dual gate IGZO TFTs were investigated. The asymmetric electrical properties and photo sensitivity under top gate and bottom gate operation is attributed to the variation of gate control region. Furthermore, the obvious asymmetric photo sensitivity can be utilized to the In-cell touch panel technology and lower the process cost compared with the traditional a-Si TFTs due to the elimination of black matrix.

Les cellules photovoltaïques en couches minces de silicium cristallin sont des candidates prometteuses pour les développements futurs de l’industrie photovoltaïque, au travers des réductions de coûts attendues et des applications dans les modules souples. Pour devenir compétitive, la filière des couches minces de silicium monocristallin doit se différencier des filières classiques. Elle est donc généralement basée sur l’épitaxie de couches de haute qualité puis sur le transfert de ces couches vers un support mécanique pour terminer la fabrication de la cellule et réutiliser le premier substrat de croissance. Le but de cette thèse est de trouver les associations technologiques qui permettent de réaliser des cellules photovoltaïques en couches minces et ultra-minces de silicium monocristallin à haut-rendement. Les travaux présentés s’articulent selon deux axes principaux : le développement et la maîtrise de procédés technologiques pour la fabrication de cellules solaires en couches minces et l’optimisation des architectures de cellules minces haut-rendement.Dans ce cadre de travail, les développements des techniques de fabrication ont d’abord concerné la mise au point de procédés de transfert de couches minces : une technologie basse température de soudage laser et un soudage par recuit rapide haute température. Afin d’augmenter le rendement de conversion, nous avons développé des structurations de surface utilisant les concepts de la nano-photonique pour améliorer le pouvoir absorbant des couches minces. Avec une lithographie interférentielle à 266 nm et des gravures sèches par RIE et humides par TMAH (Tetramethylammonium Hydroxide), nous pouvons réaliser des cristaux photoniques performants sur des couches épitaxiées de silicium. Finalement, nous avons pu concevoir des architectures optimisées de cellules solaires minces à homo-jonction de silicium et à hétéro-jonction silicium amorphe / silicium cristallin plus performantes électriquement, grâce aux outils de simulation électro-optique. Notre approche théorique nous a aussi conduits à expliciter les phénomènes électriques propres aux couches minces, et à démontrer tout le potentiel des cellules photovoltaïques minces en silicium monocristallin. / Thin-film crystalline silicon solar cells are promising candidates for future developments in the photovoltaic industry, through expected costs reductions and applications in flexible modules. To be competitive, thin-film monocrystalline silicon solar cell technology must differentiate itself from conventional ones. It is generally based on the epitaxy of high-quality layers and then on the transfer of these layers onto a mechanical support to complete the manufacture of the cell and reuse the growth substrate. The aim of this thesis is to find the technological associations that make it possible to realize high-efficiency photovoltaic cells from thin and ultra-thin layers of monocrystalline silicon. The work presented focuses on two main axes: the development and control of technological processes for the fabrication of thin-film solar cells and the optimization of high-performance thin-cell architectures.In this framework, the development of manufacturing techniques began with the development of thin-film transfer processes: low temperature laser welding technology and high temperature fast annealing welding technology. In order to increase conversion efficiency, we have developed surface patterns using the nano-photonics concepts to improve the absorbency of thin films. With an interferential lithography at 266 nm and dry etching by RIE and wet etching by TMAH (Tetramethylammonium Hydroxide), we can produce high-performance photonic crystals on epitaxial layers of silicon. Finally, we were able to design optimized architectures of thin solar cells with homo-junction of silicon and hetero-junction amorphous silicon / crystalline silicon more efficient electrically, thanks to electro-optical simulation tools. Our theoretical approach has also led us to explain the electrical phenomena specific to thin films, and to demonstrate the full potential of thin photovoltaic cells made of monocrystalline silicon.

Ce manuscrit présente l'étude de la fabrication de couches minces de silicium basée sur des différents types de dépôt chimique en phase vapeur assisté par plasma (PECVD) pour des applications dans le photovoltaïque. Tout d'abord, nous avons combiné une chimie du plasma halogéné en utilisant un mélange de SiF4/H2 et la technique plasmas distributés matriciellement à résonance cyclotronique électronique (MDECR) PECVD pour le dépôt de μc-Si:H à grande vitesse. Nous trouvons que les conditions d'énergie ionique modérée sont bénéfiques pour obtenir une diminution significative de la densité des nano-vides, et ainis nous pouvons obtenir un matériaux de meilleure qualité avec une meilleure stabilité. Une méthode de dépôt en deux étapes a été introduite comme moyen alternatif d'éliminer la formation d'une couche d'incubation amorphe pendant la croissance du film. Ensuite, nous avons exploré la technique d'excitation Tailored Voltage Waveform (TVW) pour les processus plasma radiofréquence capacitivement couplé (RF-CCP). Grâce à l'utilisation de TVW, il est possible d'étudier indépendamment l'influence de l'énergie ionique sur le dépôt de matériaux à une pression de processus relativement élevée. Basé sur ce point, nous avons étudié le dépôt de μc-Si:H et a-Si:H à partir des plasma de SiF4/H2/Ar et de SiH4/H2, respectivement. A partir d'une analyse des propriétés structurelles et électroniques, nous constatons que la variation de l'énergie ionique peut directement traduite dans la qualité du matériaux. Les résultats se sont appliqués aux dispositifs photovoltaïques et ont établi des liens complets entre les paramètres de plasma contrôlables par TVW et les propriétés de matériaux déposé, et finalement, les performances du dispositif photovoltaïque correspondant. Enfin, nous avons trouvé que dans le cas du dépôt de couches minces de silicium à partir du plasma de SiF4/H2/Ar à l'aide de sawtooth TVW, on peut réaliser un processus de dépôt sur une électrode, sans aucun dépôt ou gravure. contre-électrode. Ceci est dû à deux effets: la nature multi-précurseur du processus de surface résultant et la réponse de plasma spatiale asymétrique par l'effet d'asymétrie de pente de la sawtooth TVW. La découverte de tels procédés “electrode-selective” encourage la perspective que l'on puisse choisir un ensemble de conditions de traitement pour obtenir une grande variété de dépôts désirés sur une électrode, tout en laissant l'autre vierge. / This thesis describes the study of silicon thin film materials deposition and the resulting photovoltaic devices fabrication using different types of plasma-enhanced chemical vapour deposition (PECVD) techniques.In the first part, we combine a SiF4/H2 plasma chemistry with the matrix-distributed electron cyclotron resonance (MDECR) PECVD to obtain high growth rate microcrystalline silicon (µc-Si:H). Due to the special design of MDECR system, careful investigation of the impact energy of impinging ions to material deposition can be accessible. We find that moderate ion energy conditions is beneficial to achieve a significant drop in the density of nano-voids, thus a higher quality material with better stability can be obtained. A two-step deposition method is introduced as an alternative way to eliminate the existence of amorphous incubation layer during film growth.The second part of work is dedicate to the exploration of the Tailored Voltage Waveforms (TVWs) excitation technique for capacitively coupled plasmas (CCP) processes. As an advantage over the conventional sinusoidal excitations, TVWs technique provide an elegant solution for the ion flux-energy decoupling in CCP discharges through the electrical asymmetry effect, which makes the independent study of the impact of ion energy for material deposition at relatively high process pressure possible. Based on this insight, we have studied the deposition of µc-Si:H and amorphous silicon (a-Si:H) from the SiF4/H2/Ar and SiH4/H2 plasma chemistry, respectively. From the structural and electronic properties analysis, we find that the variation of ion energy can be directly translated into the material quality. We have further applied these results to photovoltaic applications and established bottom-up links from the controllable plasma parameters via TVWs to the deposited material properties, and eventually to the resulting device quality.In the last part, as a further application of TVWs, an “electrode-selective” effect has been discovered in the CCP processes. In the case of silicon thin film deposition from the SiF4/H2/Ar plasma chemistry, one can achieve a deposition process on one electrode, while at the same time either no deposition or an etching process on the counter electrode. This is due to two effects: the multi-precursor nature of the resulting surface process and the asymmetric plasma response through the utilization of TVWs. Moreover, such deposition/etching balance can be directly controlled through H2 flow rate. From a temporal asymmetry point of view, we have further studied the impact of process pressure and reactor geometry to the asymmetric plasma response for both the single-gas and multi-gas plasmas using the sawtooth waveforms. The product of pressure and inter-electrode distance P·di is deduced to be a crucial parameter in determine the plasma heating mode, so that a more flexible control over the discharge asymmetry as well as the relating “electrode-selective” surface process can be expected.

Le domaine du photovoltaïque en couches minces s’attache à réduire le coût de l’énergie photovoltaïque, en réduisant considérablement la quantité de matières premières utilisées. Dans le cas du silicium cristallin en couches minces, la réduction de l’épaisseur de la cellule s’accompagne d’une baisse drastique de l’absorption, notamment pour les plus fortes longueurs d’onde. Nombreuses sont les techniques aujourd’hui mises en œuvre pour lutter contre cette baisse de performance, dont l’utilisation des effets plasmoniques induits par des nanostructures métalliques qui permettent un piégeage de la lumière accru dans la couche absorbante. Dans ces travaux, nous étudions l’influence de nanostructures d’argent organisées suivant un réseau périodique sur l’absorption d’une couche de silicium. Ces travaux s’articulent autour de deux axes majeurs. L’influence de ces effets plasmoniques sur l’absorption est d’abord mise en évidence à travers différentes simulations numériques réalisées par la méthode FDTD. Nous étudions ainsi les cas de réseaux périodiques finis et infinis de nanostructures d’argent situés sur la face arrière d’une couche mince de silicium. En variant les paramètres du réseau, nous montrons que l’absorption au sein du silicium peut être améliorée dans le proche infrarouge, sur une large plage de longueurs d’onde. Le second volet de la thèse concerne la réalisation des structures modélisées. Pour cela, deux voies de fabrication ont été explorées et développées. Pour chacune d’entre elles, trois briques élémentaires ont été identifiées : (i) définition du futur motif du réseau grâce à un masque, (ii) réalisation de pores dans le silicium et (iii) remplissage des pores par de l’argent pour former le réseau métallique. La première voie de fabrication développée fait appel à un masque d’alumine, réalisé par l’anodisation électrochimique d’une couche d’aluminium, pour définir les dimensions du réseau métallique. Une gravure chimique assistée par un métal est ensuite utilisée pour former les pores, qui seront alors comblés grâce à des dépôts d’argent par voie humide. La seconde voie de fabrication utilise un masque réalisé par lithographie holographique, une gravure des pores par RIE et un remplissage des pores par dépôt d’argent electroless. Les substrats plasmoniques fabriqués sont caractérisés optiquement, au moyen d’une sphère intégrante, par des mesures de transmission, réflexion et absorption. Pour tous les substrats plasmoniques caractérisés, les mesures optiques montrent une baisse de la réflexion et de la transmission et une hausse de l’absorption pour les plus grandes longueurs d’onde. / Thin-film photovoltaics focus on lowering the cost reduction of photovoltaic energy through the significant reduction of raw materials used. In the case of thin-films crystalline silicon, the reduction of the thickness of the cell is linked to a drastic decrease of the absorption, particularly for the higher wavelengths. This decrease of the absorption can be fought through the use of several different light trapping methods, and the use of plasmonic effects induced by metallic nanostructures is one of them. In this work, we study the influence of a periodic array of silver nanostructures on the absorption of a silicon layer. This work is decomposed into two main axes. First, the influence of the plasmonic effects on the silicon absorption is highlighted through different numerical simulations performed by the FDTD method. Both finite and infinite arrays of silver nanostructures, located at the rear side of a thin silicon layer, are studied. By varying the parameters of the array, we show that the silicon absorption can be improved in the near infrared spectral region, over a wide range of wavelengths. The second part of the thesis is dedicated to the fabrication of such modeled structures. Two different approaches have been explored and developed inside the lab. For each of these two strategies, three major building blocks have been identified: (i) definition of the future array pattern through a mask, (ii) etching of the pattern in the silicon layer and (iii) filling of the pores with silver in order to form the metallic array of nanostructures. In the first fabrication method, an anodic alumina mask, produced by the electrochemical anodization of an aluminium layer, is used in order to define the dimensions of the metallic array. A metal assisted chemical etching is then performed to produce the pores inside the silicon, which will then be filled with silver through a wet chemical process. The second fabrication method developed involves the use of holographic lithography to produce the mask, the pores in silicon are formed by reactive ion etching and they are filled during an electroless silver deposition step. The fabricated plasmonic substrates are optically characterized using an integrating sphere, and transmission, reflection and absorption are measured. All the characterized plasmonic substrates shown a decrease of their reflection and transmission and an absorption enhancement at the largest wavelengths.