<p>  </p> <p>Silicon carbide (SiC) is a ceramic material of interest for many applications due to its mechanical properties, oxidation resistance, and high thermal conductivity. However, one limitation of SiC is its low fracture toughness. There is evidence that SiC with crystallographic texture and an anisotropic microstructure of aligned plate-shaped grains has improved fracture toughness without sacrificing strength. Previous techniques to create these materials have made use of either pressure during densification or a strong magnetic field, but these processes limit possible geometries that can be created. In this dissertation, the additive manufacturing technique direct ink writing (DIW) and pressureless templated grain growth (TGG) are proposed as a route to complex-shaped textured SiC. </p> <p><br></p> <p>DIW is a colloidal processing technique where ceramic suspensions are extruded through a nozzle along a path, building up a part layer-by-layer. High aspect ratio particles can be aligned via the forces in the print nozzle. In this work, single crystal SiC platelet seed particles were added to a SiC suspension and aligned with DIW. After densification, samples were annealed above the sintering temperature. During annealing, TGG occurs where the platelet seed particles grow at the expense of the finer matrix particles, and this results in crystallographic texture. </p> <p><br></p> <p>First, work on the development of the DIW process for the creation of textured SiC is shown. Aqueous SiC suspensions were developed with a high solids loading (> 50 vol%) and low polymer content (< 5 vol%) to maximize the density achieved during sintering, which is ideal for TGG. Four rheological parameters (viscosity of the suspension at 5 s­-1, zero shear viscosity, oscillatory yield stress, and equilibrium storage modulus) were related to the amount of viscosity modifying polymer (polyvinylpyrrolidone) and observed quality of prints. The best prints were made from suspensions that had a viscosity of 30-35 Pa s, ZSV of 5000-7000 Pa s, and yield stress 100-150 Pa. The best suspension for printing was identified to be 53 vol% solids with 0.2 vol% PVP due to its high particle loading and ability to create consistent prints. The addition of 5 vol% platelet particles to the suspension did not impact the rheology or printability significantly.</p> <p><br></p> <p>Next, textured SiC ceramics over 95% theoretical density were created via pressureless sintering and annealing. Samples were fabricated with and without 5 vol% platelet seeds, and with and without annealing at 2050 ºC and 2150 ºC. The effects of DIW, seed particles, and annealing temperature on the microstructure and crystallographic texture are presented. Annealing lead to the development of large, high aspect ratio plate-shaped grains among a matrix of many finer, low aspect ratio grains. Higher annealing temperatures and addition of platelet seeds both increased the size of the large grains. Samples were found to be textured regardless of having platelet seeds. Via x-ray diffraction and electron backscatter diffraction, unseeded SiC was found to have texture where the crystallographic direction [0001] had a preferred orientation perpendicular to the normal direction. This occurred for both DIW and cast SiC, so the texture development must have occurred during sintering, though the mechanism is unknown. For seeded SiC, platelet seeds aligned in DIW successfully seeded the grain growth to develop crystallographic texture. The texture was mainly influenced by the alignment of platelet seed particles via shear stresses in the print nozzle, causing a one-dimensional texture where [0001] is perpendicular to the printing direction. However, it was found that the texture was not the expected one-dimensional, concentric alignment of platelet particles in DIW, so the shear stresses in the nozzle are not solely responsible for the texture developed.</p> <p><br></p> <p>Finally, the mechanical behavior of these materials was explored via 4-point flexural strength testing and Weibull analysis. The effect of texture, print orientation, and printing defects on the mechanical and fracture behavior of these materials is discussed. Mechanical tests were conducted both parallel and perpendicular to the printing direction. DIW samples were found to have a variety of defects after densification, including visible print lines, air bubbles, and porosity. Unseeded SiC annealed at 2050 ºC tested parallel to the print direction was found to have the best combination of mechanical properties among all annealed SiC, with evidence of toughening on the fracture surface, flexural strength 405 ± 16 MPa, and Weibull modulus of 15.4. Seeded SiC annealed at 2050 ºC had a high degree of transgranular fracture among large plate-shaped grains, but still had a flexural strength 339 ± 41 MPa. However, improved alignment of grains in future work may increase the incidence of intergranular fracture. At both annealing temperatures, textured SiC created with aligned platelet seed particles was found to have comparable mechanical strength to those fabricated without seed particles despite having a coarser microstructure, suggesting texture may influence the mechanical properties. </p>

Silicon-based ceramics and ceramic matrix composites (CMCs), such as silicon carbide (SiC) fiber reinforced SiC, are promising candidates for hot section components in next generation turbine engines. Environmental barrier coatings (EBCs) are essential for implementing these components as they insulate and protect the substrate from reaction with water vapor in the engine environment. EBCs are typically deposited via atmospheric plasma spraying (APS) and preparing the component surfaces through cleaning and roughening prior to coating is a vital step to ensure sufficient coating adhesion. The adhesion of a plasma sprayed coating to the underlying component is one of the most important properties as the component will not be protected if the coating is not well adhered. Surface roughening of metallic components via grit blasting is well documented and understood, but much less is known about preparing ceramic and ceramic composite surfaces for thermal spray coating. Silicon coatings are often used as a bond coating between SiC-based components and EBC top layers, but the adhesion strength of plasma sprayed Si on these substrates, Si splat formation and the factors that affect coating formation and adhesion have not been well studied. The effects of automated grit blasting process parameters on surface roughness and material loss of a reaction bonded SiC (rb SiC) composite were evaluated. Surface roughness before and after grit blasting was evaluated with a confocal laser scanning microscope. The differences and advantages of automated grit blasting compared to manual grit blasting were observed. Most notably was the level of control at high nozzle traverse speeds resulting in reduction of material loss and consistency of roughening. At high nozzle traverse speeds, the amount of material loss decreased greatly with a small effect on induced surface roughness. The degree of grit blasting induced roughness and material loss was found to be largely dependent on the nature of the composite matrix and reinforcement, as well as blast nozzle traverse speed. A statistical model was developed to predict the substrate thickness loss and induced average roughness based on nozzle traverse speed and blast pressure for automated grit blasting. Additionally, laser ablation was used to create controlled, regularly patterned surface texture on rb SiC substrates to further investigate the role of texture parameters in Si coating adhesion. Si was plasma sprayed onto rb SiC substrates to deposit both thick coatings to evaluate adhesion strength and single splats to study splat formation. Surface roughness/texture, substrate preheat temperature and mean Si particle size were varied in plasma spray coating experiments to observe their role in coating adhesion strength. Si adhesion strength was found to be related to all three factors and a statistical model was developed to predict adhesion strength based on them. Substrate preheat temperature had a significant effect on both Si adhesion strength and Si splat formation on rb SiC. Single splat formation during plasma spraying of Si on SiC was simulated with software called SimDrop. Simulations of Si droplet impact, spreading and solidification during plasma spraying on smooth and textured SiC surfaces were used to investigate the effects of relevant process parameters on splat formation. Experimentally observed Si splats on smooth substrates at different temperatures during deposition were matched with simulated splats with the same spraying parameters. A change in thermal contact resistance with changing substrate preheat temperature was confirmed by the simulation results. The role of surface texture parameters for a regularly patterned surface texture in splat formation was demonstrated through simulation. This dissertation investigates methods of roughening and preparing a SiC composite substrate for plasma spray coating, as well as factors which affect the adhesion strength and splat formation of plasma sprayed Si through experiments and simulation. The observations made provide valuable insight for understanding and optimizing the manufacturing processes utilized to deposit strongly adhered coatings onto SiC-based composites. In addition, areas of interest in this field for future study and further investigation are introduced and suggested. / Doctor of Philosophy / Silicon-based ceramics and ceramic matrix composites (CMCs), such as silicon carbide (SiC) fiber reinforced SiC, are promising candidates for hot section components in next generation turbine engines. Environmental barrier coatings (EBCs) are essential for implementing these components as they insulate and protect the substrate from reaction with water vapor in the engine environment. EBCs are typically deposited via atmospheric plasma spraying (APS) and preparing the component surfaces through cleaning and roughening prior to coating is a vital step to ensure sufficient coating adhesion. The adhesion of a plasma sprayed coating to the underlying component is one of the most important properties as the component will not be protected if the coating is not well adhered. Silicon coatings are often used as a bond coating between SiC-based components and EBC top layers, but the adhesion strength of plasma sprayed Si on these substrates, Si splat formation and the factors that affect coating formation and adhesion have not been well studied. This dissertation investigates methods of roughening and preparing a SiC composite substrate for plasma spray coating, as well as factors which affect the adhesion strength and splat formation of plasma sprayed Si through experiments and simulation. The observations made provide valuable insight for understanding and optimizing the manufacturing processes utilized to deposit strongly adhered coatings onto SiC-based composites. In addition, areas of interest in this field for future study and further investigation are introduced and suggested.

As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors. / Doctor of Philosophy / Power conversion technology is being integrated into industrial and commercial applications with the increased use of laptops, server centers, electric vehicles, and solar and wind energy generation. Each of these converters requires the power semiconductor devices to convert energy reliably and safely. textcolor{black}{Silicon has been the primary material for these devices; however,} new devices have been commercialized from both silicon carbide (SiC) and gallium nitride (GaN) materials. Although these devices are required to undergo qualification testing, the standards were developed for silicon technology. The performance of these new devices offers many additional benefits such as physically smaller dimensions, greater power conversion efficiency, and higher thermal operating capabilities. To facilitate the increased integration of these devices into industrial applications, greater robustness and reliability analyses are required to supplement the traditional tests. The work presented here provides two new experimental methodologies to test the robustness of both SiC and GaN power transistors. These methodologies are oriented around hard-switching environments where both high voltage biases and high conduction current exist and stress the intrinsic semiconductor properties. Experimental evaluations were conducted of both material technologies where the electrical properties were monitored over time to identify any degradation effects. Additional analyses were conducted to determine the physics-oriented failure mechanisms. This work provides insight into the limitations of these semiconductor devices for both device designers and manufacturers as well as power electronic system designers.

Three-phase rectifiers/inverters are widely used in grid-tied applications. Take the electric vehicle (EV) charging systems as an example. Within a certain space designated for the chargers, quick charging yet high efficiency are demanded. According to the current industry practice, with a power rating between 10 and 30 kW, the power density are limited by silicon (Si) power semiconductor devices, which make the systems operate at only up to around 30 kHz. The emerging wide bandgap (WBG) power semiconductor devices are considered as game changing devices to exceed the limits brought by their Si counterparts. Much higher switching frequency, higher power density and higher system efficiency are expected to be achieved with WBG power semiconductor devices. Among different types of WBG power semiconductor devices, Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors (SiC MOSFETs) are more popular in current research conducted for tens of kW power converter applications. However, the commonly adopted hard switching operation in this application still leads to significant switching loss at high frequency operation even for SiC-based systems. With the unique feature that the turn-off energy is almost negligible compared with the turn-on energy, critical conduction mode (CRM) based zero voltage soft switching turn-on operation is preferred for the SiC MOSFETs to eliminate the turn-on loss with small penalty on the conduction loss and on the turn-off loss. With this soft switching operation, switching frequency of SiC-based systems is able to be pushed to more than ten times higher than Si-based systems, and therefore higher power density yet even higher system efficiency can be achieved. The CRM-based soft switching is applied to three-phase rectifiers/inverters under the unity power factor operating condition first. Decoupled CRM-based control is enabled, and the inherent drawback of wide switching frequency variation range at CRM-based operation is overcome by the proposed novel modulation technique. It is the first time that CRM-based soft switching modulation is demonstrated in the most conventional three-phase H-bridge ac–dc converter, and more than three-time size reduction compared with current industry practice yet 99.0% peak efficiency are achieved at above 300 kHz switching frequency operation. Then this proposed soft switching modulation technique is extended to non-unity power factor operating conditions especially for grid-tied inverter system applications. With several improvements on the modulation, a generalized CRM-based soft switching modulation technique is proposed, which is applicable to both the unity and non-unity power factor conditions. With the power factor down to 0.8 lagging or leading according to commercial products, above 98.0% peak efficiency is achieved with the generalized soft switching modulation technique at above 300 kHz switching frequency operation. Furthermore from the aspect of electromagnetic interference (EMI), compared with the traditional Si-based design, CRM operation brings higher differential-mode (DM) EMI noise, and higher dv/dt with SiC MOSFETs brings higher common-mode (CM) EMI noise. What's more, hundreds of kHz switching frequency operation makes the main components of the system EMI spectrum located within the frequency range related to the EMI standard (150 kHz – 30 MHz). Therefore, several methods are adopted for the reduction of EMI noise. The total inductor current ripple is reduced with multi-channel interleaving control in order to reduce DM EMI noise. The balance technique is applied in order to reduce CM EMI noise. With PCB winding coupled inductors, the well-controlled parasitic parameters make the balance technique able to be effective for a uniform reduction of CM EMI noise from 150 kHz to above 20 MHz. In addition, PCB winding based magnetic designs are beneficial to achieving manufacture automation and reducing the labor cost. / Doctor of Philosophy / Power electronics and power conversion are crucial to many applications related to electricity, such as consumer electronics, domestic and commercial appliances, automobiles, data centers, utilities and infrastructure. In today's market, quality and reliability are usually considered as a given; high efficiency (low loss), high power density (small size and weight) and low cost are the main focuses in the design of power electronics products. In the past several decades, significant achievements in power electronics have been witnessed thanks to the silicon (Si) semiconductor technology, especially the Si power semiconductor devices. Nowadays, the development of Si power semiconductor devices is already close to the theoretical limits of the material itself. Therefore, in order to meet the increasing demands from customers in different applications, wide bandgap (WBG) based power semiconductor devices, namely Gallium Nitride (GaN) and Silicon Carbide (SiC), are becoming attractive because of its great potential compared with their Si counterparts. In literature, great contributions have already been made to understanding the WBG based power semiconductor devices. It is exciting and encouraging that some of the GaN-based power electronics products featuring high efficiency, high power density and low cost have been commercialized in consumer electronics applications. However, when pursuing these objectives, previous literature has not shown any applications of high frequency soft switching technology into the high power ac–dc conversion (usually three-phase ac–dc) in a simple way as the low power ac–dc conversion (usually single-phase ac–dc) in consumer electronics products. The key to achieving high efficiency, high power density and low cost is the high frequency soft switching operation. For single-phase ac–dc systems, the research on the realization of soft switching by control strategies instead of additional physical complexity has been intensively conducted, and this technology has also been adopted in the current industry practice. Therefore, the major achievement of this work is the development of a generalized soft switching control strategy for three-phase ac–dc systems, without adding any physical complexity, which is applicable to the simplest and most conventional three-phase ac-dc circuit topology. The proposed soft switching control strategy features bidirectional (rectifiers/inverters) power conversion, active/reactive power transfer, grid-tied/stand-alone modes, and scalability to multi-channel interleaved operation. Furthermore, with high frequency, the integration of magnetic components with embedded windings in the printed circuit board (PCB) becomes feasible, which is also beneficial to achieving electromagnetic compatibility (EMC) and manufacture automation. Based on the proposed control strategy and design methodology, a SiC-based 25-kW three-phase high frequency soft switching rectifier/inverter is developed for various applications such as electric vehicle (EV) charging stations, uninterruptible power supplies (UPS) and renewable energy based utilities.

With the increasing demand for clean and renewable energy, new distribution network concepts, such as DC microgrids and distributed power generation networks, are being developed. One key component of such networks is the grid-interfacing DC-DC power converter that can transfer power bi-directionally while having a wide range of voltage step-up and step-down capabilities. Also, with the proliferated demand for electric vehicle chargers, battery energy storage systems, and solid-state transformers (SST), the bi-directional high-power DC-DC converter plays a more significant role in the renewable energy industry. To satisfy the requirements of the high-power bi-directional wide-range DC-DC converter, different topologies have been compared in this thesis, and the four-switch buck-boost (FSBB) converter topology has been selected as the candidate. This work investigates the operation principle of the FSBB converter, and a digital real-time low-loss quadrangle current mode(QCM) control implementation, which satisfies the zero-voltage-switching (ZVS) requirements, is proposed. With the QCM control method, the FSBB converter efficiency can be further increased by reducing the inductor RMS current and device switching loss compared to traditional continuous current mode(CCM) control and discontinuous current mode(DCM) control. Although the small signal model has been derived for FSBB under CCM control, the small ripple approximation that was previously used in the CCM model no longer applies in the QCM model and causing the model to be different. To aid the control system compensator design, QCM small signal model is desired. In this thesis, a small signal model for FSBB under QCM control is proposed. A 50 kW silicon carbide (SiC) based grid-interfacing converter prototype was constructed to verify the QCM control implementation and small signal model of the FSBB converter. For driving the 1.2kV SiC modules, an enhanced gate driver with fiber optic (FO) based digital communication capability was designed. Digital on-state and off-state drain-source voltage sensors and Rogowski coil-based current sensors are embedded in the gate driver to minimize the requirement for external sensors, thus increasing the power density of the converter unit. Also, Rogowski-coil-based current protection and drain-source voltage-based current protection is embedded in the gate driver to prevent SiC switching device from damage. / Master of Science / The renewable energy sector is driving the development of new distribution networks, such as DC microgrids and distributed power generation networks. One crucial component of these networks is the grid-interfacing DC-DC power converter, which can transfer power in both directions while maintaining a wide voltage range. This study evaluates various topologies and selects the four-switch buck-boost (FSBB) converter topology to meet the demands of high-power, bi-directional, and wide-range DC-DC converters. This work analyzed the operation of the FSBB converter and proposed a novel simplified quadrangle current mode (QCM) control implementation. With the QCM control method, the FSBB converter efficiency can be further improved by reducing losses compared to conventional control methods. This study also provides a small signal model, which can be used to aid the control loop compensator design where application of FSBB converter is required. A 50 kW silicon carbide (SiC) based grid-interfacing converter prototype, which was constructed to validate the proposed QCM control implementation and small signal model of the FSBB converter. As part of the converter unit,the enhanced gate driver design and implementation is presented in this thesis. This gate driver is designed with fiber optic-based digital communication, drives the wide bandgap SiC modules. The gate driver also features embedded digital on-state and off-state drain-source voltage sensors and non-intrusive current sensors to minimize external sensor requirements, thereby increasing the power density of the converter unit. The gate driver also incorporates high bandwidth current protection and drain-source voltage-based current protection to protect the SiC switching device from damage.

Silicon carbide (SiC) power switching devices promise to be a major breakthrough for new generation ac three-phase power converters, offering increased junction temperature, low specific on-resistance, fast switching, and low switching loss. These characteristics are desirable for increasing power density, providing faster system dynamics, and improving power quality. At present, the normally-on SiC JFET prototypes available from SiCED are the first SiC power switches close to commercialization. The objective of this work is to characterize the switching behavior of the prototype SiC JFET devices, as well as demonstrate the feasibility of achieving high switching frequency for a 2 kVA three-phase converter. The switching characterization of the 1200 V SiC JFET prototypes is shown for a wide range of operating conditions such as switched voltage, switched current, and junction temperature. The SiC JFET is shown to be a fast-switching, low-loss device offering performance benefits compared to traditional silicon (Si) power devices of similar ratings. Utilizing the SiC JFET, a three-phase ac buck rectifier is then demonstrated with a 150 kHz switching frequency and a rated power of 2 kVA. Additionally, improvements are made to the charge control scheme for the buck rectifier allowing power factor compensation and reduction of input current transients. / Master of Science

This work investigates three-dimensional power loop layout for application to a SiC based matrix converter, providing a symmetric, low-inductance solution. The thesis presents various layout types to achieve this design target, and details the implementation of a hybrid layout to the matrix converter phase-leg. This layout is more easily achievable with a surface-mount device package, which also offers benefits such as ease in manufacturing, and a compact package. In order to implement a surface-mount device, a PCB thermal management strategy should be utilized. An evaluation of these methods is also presented in the work. The final power loop solution that implements an aluminum nitride inlay is evaluated through simulated parasitic extraction and experimental double pulse tests. The layout achieves small, symmetric loop inductances. Finally, the full power, three-phase matrix converter demonstrates the successful implementation of this power loop layout. / Master of Science / In the United States, 40% primary energy consumption comes from electricity generation, which is the fastest growing form of end-use energy. Industries such as commercial airlines are increasing their use of electric energy, while phasing out the mechanical and pneumatic aircraft components, as they offer better performance and lower cost. Thus, implementation of high efficiency, electrical system can reduce energy consumption, fuel consumption and carbon emissions [1]. As more systems rely on this electric power, the conversion from one level of power (voltage and current) to another, is critical. In the quest to develop high efficiency power converters, wide bandgap semiconductor devices are being turned to. These devices, specifically Silicon Carbide (SiC) devices, offer high temperature and high voltage operation that a traditional Silicon (Si) device cannot. Coupled with fast switching transients, these metal oxide semiconductors field effect transistors (MOSFETs), could provide higher levels of efficiency and power density. This work investigates the benefits of a three-dimensional (3D) printed circuit board (PCB) layout. With this type of layout, a critical parasitic – inductance – can be minimized. As the SiC device can operate at high switching speeds, they incur higher di/dt, and dv/dt slew rates. If trace inductance is not minimal, overshoots and ringing will occur. This can be addressed by stacking PCB traces on top of one another, the induced magnetic field can be reduced. In turn, the system inductance is lowered as well. The reduction of this parameter in the system, reduces the overshoot and ringing. This particular work applies this technique to a 15kW matrix converter. This converter poses a particular design challenge as there are a large number of devices, which can lead to longer, higher inductance PCB traces. The goal of this work is to minimize the parasitic inductance in this converter for high efficiency, high power density operation.

A finite element analysis (FEA) driven, automated numerical optimization technique is used to design electric field grading structures in a PCB-integrated bus bar for a 10 kV bondwire-less silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, careful design of field-grading structures inside the bus bar is required to mitigate the high electric field strength in the air. Using Bayesian optimization and a new weighted point-of-interest (POI) cost function, the highly non-uniform electric field is efficiently optimized without the use of field integration, or finite-difference derivatives. The proposed optimization technique is used to efficiently characterize the performance of the embedded field grading structure, providing insights into the fundamental limitations of the system. The characterization results are used to streamline the design and optimization of the bus bar and high-density module interface. The high-density interface experimentally demonstrated a partial discharge inception voltage (PDIV) of 11.6 kV rms. When compared to a state-of-the-art descent-based optimization technique, the proposed algorithm converges 3x faster and with 7x smaller error, making both the field grading structure and the design technique widely applicable to other high-density high-voltage design problems. / M.S. / Innovation trends in electrical engineering such as the electrification of consumer and commercial vehicles, renewable energy, and widespread adoption of personal electronics have spurred the development of new semiconductor materials to replace conventional silicon technology. To fully take advantage of the better efficiency and faster speeds of these new materials, innovation is required at the system-level, to reduce the size of power conversion systems, and develop converters with higher levels of integration. As the size of these systems decreases, and operating voltages rise, the design of the insulation systems that protect them becomes more critical. Historically, the design of high-density insulation system requires time-consuming design iteration, where the designer simulates a case, assesses its performance, modifies the design, and repeats, until adequate performance is achieved. The process is computationally expensive, time-consuming, and the results are not easily applied to other insulation design problems. This work proposes an automated design process that allows for the streamlined optimization of high-density insulation systems. The process is applied to a 10 kV power module and experimentally demonstrates a 38\% performance improvement over manual design techniques, while providing an 8 times reduction in design cycle time.

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第25291号 / 工博第5250号 / 新制||工||1999(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 木本 恒暢, 教授 引原 隆士, 准教授 三谷 友彦, 教授 川上 養一 / 学位規則第4条第1項該当 / Doctor of Agricultural Science / Kyoto University / DFAM

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第25295号 / 工博第5254号 / 新制||工||2000(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 白石 誠司, 准教授 船戸 充 / 学位規則第4条第1項該当 / Doctor of Agricultural Science / Kyoto University / DFAM