Developing a flexible receiver, which can be reconfigured to multiple standards, is the key to solving the problem of embedding numerous and ever-changing functionalities in mobile handsets. Difficulty in efficiently reconfiguring analog blocks of a receiver chain to multiple standards calls for moving the ADC as close to the antenna as possible so that most of the processing is done in DSP. Different standards are sampled at different frequencies and a programmable anti-aliasing filtering is needed here. Windowed integration samplers have an inherent sinc filtering which creates nulls at multiples of fs. The attenuation provided by sinc filtering for a bandwidth B is directly proportional to the sampling frequency fs and, in order to meet the anti-aliasing specifications, a high sampling rate is needed. ADCs operating at such a high oversampling rate dissipate power for no good use. Hence, there is a need to develop a programmable discrete-time down-sampling circuit with high inherent anti-aliasing capabilities. Currently existing topologies use large numbers of switches and capacitors which occupy a lot of area.A novel technique in reducing die area on a discrete-time sinc2 ↓2 filter for charge sampling is proposed. An SNR comparison of the conventional and the proposed topology reveals that the new technique saves 25 percent die area occupied by the sampling capacitors of the filter. The proposed idea is also extended to implement higher downsampling factors and a greater percentage of area is saved as the down-sampling factor is increased. The proposed filter also has the topological advantage over previously reported works of allowing the designers to use active integration to charge the capacitance, which is critical in obtaining high linearity. A novel technique to implement a discrete-time sinc3 ↓2 filter for windowed integration samplers is also proposed. The topology reduces the idle time of the integration capacitors at the expense of a small complexity overhead in the clock generation, thereby saving 33 percent of the die area on the capacitors compared to the currently existing topology. Circuit Level simulations in 45 nm CMOS technlogy show a good agreement with the predicted behaviour obtained from the analaysis.

ITC/USA 2014 Conference Proceedings / The Fiftieth Annual International Telemetering Conference and Technical Exhibition / October 20-23, 2014 / Town and Country Resort & Convention Center, San Diego, CA / This paper describes a system framework for a multi-band, multi-mode software defined radio (MBMM SDR) being developed for next-generation telemetry applications. The system framework consists of the multi-band front-end (MBFE), the multi-mode digital radio (MMDR), and the configuration and control (C2) sub-systems. The MBFE consists of an L/S/C-band transceiver architecture that provides wideband operation, band selection, and channel tuning. The MMDR consists of the software and firmware components for high-speed digital signal processing for the telemetry waveforms. Finally, the C2 consists of the software and hardware components for system configuration, control and status. The MBFE is implemented as a standalone hardware sub-system, while the MMDR and C2 are integrated into a single hardware subsystem that utilizes state-of-the-art system-on-chip (SoC) technology. Design methodologies, hardware architectures, and system tradeoffs are highlighted to meet next-generation telemetry requirements for improved spectrum efficiency and utilizations. Approved for public release; distribution is unlimited (412TW-PA-14281).

An open systems architecture (OSA) is one in which all of the interfaces are fully defined, available to the public, and maintained according to a group consensus. One approach to achieve this is to use modular hardware and software and to buy commercial, off-the-shelf and commodity hardware. Benefits of an OSA include providing easy access to the latest technological advances in both hardware and software, enabling net-centric operations, and allowing a flexible design that can easily change as the needs of customers may change. This paper will provide details of an OSA system designed for a telemetry receiver and list the benefits of OSA for the telemetry community.

Software defined radio (SDR) introduces endless possibilities for future communication technologies. Instead of being limited to a static segment of the radio spectrum, SDR allows RF front-ends to be more flexible by using digital signal processing (DSP) and cognitive techniques to integrate adaptive hardware with dynamic software. We present the design and implementation of an innovative RF front-end transceiver architecture for application into a SDR test-bed platform. System-level requirements were extracted from the Space Network User Guide (SNUG). Initial system characterization demonstrated image leakage due to poor filtering and mixer isolation issues. Hence, the RF front-end design was re-implemented using the Weaver architecture for improved image rejection performance.

In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time transmitter and receiver system is implemented in order to measure performance when the received signal is corrupted by both Additive White Gaussian Noise and Flat Fading. The Timing Error Detection algorithm implemented is a discrete time maximum likelihood one known as FFML1, developed at Canterbury University. FFML1 along with other components of the Digital Phase Locked loop are implemented entirely in software, using Motorola 56321 assembly language.

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals.

Variable digital filters (VDF) find many application areas in communication, audio, speech and image processing. This thesis analyzes design and implementation of FIR digital filters with variable frequency characteristics and introduces two design methods. The design and implementation of the proposed methods are realized on Matlab software program. Various filter design examples and comparisons are also outlilned. One of the major application areas of VDFs is software defined radio (SDR). The interpolation problem on sample rate converter (SRC) unit of the SDR is solved by using these filters. Realizations of VDFs on SRC are outlined and described. Simulations on Simulink and a specific hardware are examined.

The main purpose of this thesis work is to find and compare different network characteristics of MPS (Mobile Positioning System) in the different wireless technology domains. Since decades ago MNO’s (Mobile Network Operators) added many new services based on the geographical areas of subscribers and their needs. Here we define wireless networks and go through different types of technologies and do the comparison when they collect different types of data for their location-based services and see if we could have the same accuracy with 2G (second generation) of mobile network as like as 3G (third generation) and higher. Finally, we will come up with a proposal for new age technology.

Orientador: Prof. Dr. Carlos Eduardo Capovilla / Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Engenharia Elétrica, 2017. / Com a evolução dos meios de comunicação e a constante necessidade por altas taxas de transferencia de dados, a comunicação sem fio torna-se constantemente o principal e favorito meio para as mais diversas aplicações. Por aliar agilidade, desempenho e facilidade de instalação, é frequentemente encontrada em sistemas de controle, áudio e televisão, acesso a internet, etc. Porém, devido as imperfeições e ruído no canal, essa comunicação requer uma eficiente modulação e uma adequada proteção contra erros na transmissao dos dados. A versão IEEE 802.11g, presente em praticamente todos sistemas de comunicação moderno e amplamente difundido pelas redes conhecidas como WiFi surge como perfeita solução, pois permite alinhar técnicas robustas e efcientes, como a modulação OFDM e a codificação Convolucional. Alinhado ao conceito digital e a forma dinamica que a comunicação sem fio proporciona, o conceito de SDR (Software Dened Radio), torna-se uma interessante e poderosa ferramenta com a possibilidade de simulação e implementação de transceptores para diversas aplicaçõess em um único dispositivo. Assim, este projeto de mestrado tem como objetivo o estudo e testabilidade de um sistema IEEE 802.11g de comunicação sem fio utilizando dispositivo SDR, com foco em sistemas eficientes e de baixo custo, para fazer a interface entre o meio físico e o ambiente de processamento do sinal digital. / With the advancements of communication technology and the constant need for high rates of data transfer, wireless communication is consistently the main and favorite option for the most kind of applications. By combining agility, performance and fast installation, it is often found in control systems, audio and television systems, internet access, etc. However, due to the imperfections and noise in the channel, this communication requires an eficient modulation and an adequate protection against errors in the data transmission. The IEEE 802.11g standard, also used in practically all modern communication systems and widely difused by the networks known as WiFi, appears as a perfect solution, since it allows to align robust and eficient techniques such as OFDM modulation and Convolutional coding. Using digital concept and the dynamic behavior of wireless communication, the concept of SDR (Software Dened Radio) becomes an interesting and powerful tool because the possibility of simulation and implementation of transceivers for several applications in a single device. This project aims to make a wireless IEEE 802.11g communication system using Software Defined Radios focusing on low cost radios and high performance to make the interface between the real world and the digital signal processing.

In order to keep up with the increasing demand on speed and reliability in modern wireless systems, new standards have to be introduced. By using Multiple Input Multiple Output technology (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) technologies the performance can be increased dramatically. Forthcoming standards such as WLAN 802.11n, WiMax and 3GPP LTE are all taking advantage of MIMO technology. To perform realistic tests with these standards it is often not enough to run software simulations in for example Matlab. Instead, as many real world parameters as possible need to be included. This can be done using a testbed, like the LiUMIMO, that actually transmits and receives data through the air. The LiUMIMO is designed as a Software Defined Radio (SDR), only the RF front end and the data log are implemented in hardware, while all signal processing will be performed in Matlab.