The smart dust concept is a fairly recent phenomenon to engineering. It assumes monitoring of a real natural environment in which motes or smart dust machines swarm in collective and coordinate information among themselves and/or to a backend control platform. In analog mixed signal field work on such devices is gaining momentum such that it is conceived to be one of the emerging fields in technology, and work was only possible once the technology for fabrication touched the nanoscale regions. Smart dust network involves remote devices connected in a hive sensing burst type datum signals from the environment and relaying information amongst themselves in an energy efficient manner to coordinate an appropriate response to a detected stimulus. The project presumed a RF based communication strategy for coordination amongst the devices through a wireless medium. That is less susceptible to stringent requirements of LOS and a base band processing system that comprised of an environment sensor, an AFE module, an ADC, a DSP and a DAC. Essentially a 10 bit, 2 Mega Hertz MHz pipelined ADC implemented in a STM 65nm technology. The ADC benefits the smart dust device in allowing it to process data in an energy efficient way and also focusing on reduced complexity as itsdesign feature. While it differs in the other ADC of the system by operating at a higher frequency and assuming a different design philosophy assuming a coherent system sensitive to a clock. The thesis work assumes that various features ofenergy harvesting, regulation and power management present in the smart dustmote would enable the system to contain such a diverse ADC. The ADCs output digital datum would be compatible to the rest of the design modules consisting mainly of DSP sections. The ADC novelty is based on the fact that it removes the necessity of employing a high power consuming OpAmp whose design parameters become more complex as technology scales to the nanoscale era and further down. A systematic, bottom up, test driven approach to design is utilized and various behaviours of the system are captured in Cadence design environment with verilogto layout models and MATLAB and Simulink models.

This research work deals with the analysis, design and implementation of thyristor switched plain capacitor banks and thyristor switched shunt filter banks. Performances of various thyristor switched capacitor (TSC) topologies are also investigated by simulations. The theoretical findings have been verified by carrying out experimental work on two prototypes implemented within the scope of this research work, one is a wye-connected laboratory prototype and the other is a delta-connected application prototype integrated to some of the SVCs existing in Turkish Coal Enterprise s Plants. The advantages of back-to-back connected thyristor switches over conventional electromechanical contactors are also made clear by conducting an intensive experimental work in the laboratory. A good correlation have been obtained between theoretical and experimental results.

<p>The sigma-delta techniques for analog-to-digital conversion have for long been utilized when high precision is needed. Despite the fact that these have been realized by a numerous of different structures, the theory of how to construct a sigma-delta ADC is not very extensive.</p><p>This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator.</p><p>The first activity is to scale the inputs to each integrator in order to make sure that the produced outputs of each integrator is within the output-range of the OTA which is used. The next thing that is presented is an algorithmic way of descending from the SFG design of the modulator down to a switched-capacitor implementation of the system.</p><p>To be able to continue with the circuit realization, one needs to do a rigorous noise analysis of the modulator, which gives the sizes of the different capacitors in the SC-circuits. The last topic of this thesis is a method to obtain the specifications of the OTA in each integrator.</p>

The objective of the proposed research is to advance the power efficiency of wireless neural stimulating systems in inductively powered implantable medical devices (IMD). Several innovative system- and circuit-level techniques are proposed towards the development of power-management circuits and wireless neural stimulating systems with inductive power transmission to improve the overall stimulation power efficiency. Neural stimulating IMDs have been proven as effective therapies to alleviate neurological diseases, while requiring high power and performance for more efficacious treatments. Therefore, power-management circuits and neural stimulators in IMDs should have high power efficiencies to operate with smaller received power from a larger distance. Neural stimulating systems are also required to have high stimulation efficacy for activating the target tissue with a minimum amount of energy, while ensuring charge-balanced stimulation. These features provide several advantages such as a long battery life in an external power transmitter, extended-range inductive power transfer, efficacious and safe stimulation, and less tissue damage from overheating. The proposed research presents several approaches to design and implement the power-efficient wireless neural stimulating IMDs: 1) optimized power-management circuits for inductively powered biomedical microsystems, 2) a power-efficient neural stimulating system with adaptive supply control, and 3) a wireless switched-capacitor stimulation (SCS) system, which is a combination structure of the power-management circuits and neural stimulator, to maximize both stimulator efficiency (before electrodes) and stimulus efficacy (after electrodes).

The sigma-delta techniques for analog-to-digital conversion have for long been utilized when high precision is needed. Despite the fact that these have been realized by a numerous of different structures, the theory of how to construct a sigma-delta ADC is not very extensive. This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator. The first activity is to scale the inputs to each integrator in order to make sure that the produced outputs of each integrator is within the output-range of the OTA which is used. The next thing that is presented is an algorithmic way of descending from the SFG design of the modulator down to a switched-capacitor implementation of the system. To be able to continue with the circuit realization, one needs to do a rigorous noise analysis of the modulator, which gives the sizes of the different capacitors in the SC-circuits. The last topic of this thesis is a method to obtain the specifications of the OTA in each integrator.

The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power. In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel readout implementation in CMOS image sensors is presented. The aim of the conducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

No description available.

FundaÃÃo Cearense de Apoio ao Desenvolvimento Cientifico e TecnolÃgico / With global need to reduce energy consumption, the search for more efficient technologies has become the focus of many studies. Among these technologies, it can mention the photovoltaic solar energy and LEDs, which have shown an expansion in recent decades. Photovoltaic generation is shown as an attractive energy source because it is renewable and its raw material is practically inexhaustible. While LEDs have a promising advance in lighting and is used in several applications. To integrate these technologies, this paper proposes the study of a DC-DC step-up switched-capacitor (SC) converter for LEDs applied to photovoltaic stand-alone systems. The proposed circuit differs from other topologies SC to insert an inductor in series with the input source, which can operate in discontinuous conduction mode (DCM), reducing losses switching, or continuous conduction mode (CCM), allowing the reduction of conduction losses in the circuit. The converter is driven by the frequency modulation, which is obtained as a function of input voltage. For this reason, the current in the LEDs can be stabilized without the need for sensor or feedback. The prototype developed in the laboratory was designed for a lamp of 54 W and operating at high frequency (up to 165 kHz), allowing the reduction of the circuit volume. Experimental results of the circuit in DCM and CCM show that the converter has a high yield, validating the proposal. / Tendo em vista a tendÃncia da reduÃÃo do consumo de energia no mundo, a busca por tecnologias mais eficientes tem se tornado o foco de muitos estudos. Dentre estas tecnologias, pode-se citar a energia solar fotovoltaica e os LEDs, que vem apresentando uma expansÃo nas ultimas dÃcadas. A geraÃÃo fotovoltaica se mostra como uma atrativa fonte de energia, por ser renovÃvel e sua matÃria-prima ser praticamente inesgotÃvel. Enquanto os LEDs apresentam um avanÃo promissor na iluminaÃÃo, sendo utilizado nas mais diversas aplicaÃÃes. Visando a integraÃÃo destas tecnologias, este trabalho propÃe o estudo de um conversor CC-CC elevador com capacitor comutado (Switched Capacitor - SC) para LEDs, aplicado a sistemas fotovoltaicos autÃnomos. O circuito proposto se difere de outras topologias SC por inserir um indutor em sÃrie com a fonte de entrada, o qual pode operar no modo de conduÃÃo descontÃnua (MCD), reduzindo as perdas por comutaÃÃo, ou no modo de conduÃÃo contÃnua (MCC), possibilitando a reduÃÃo das perdas por conduÃÃo do circuito. O conversor à acionado atravÃs da modulaÃÃo por frequÃncia, a qual à obtida em funÃÃo da tensÃo de entrada. Por este motivo, a corrente nos LEDs pode ser estabilizada sem a necessidade de sensores ou de realimentaÃÃo. O protÃtipo desenvolvido em laboratÃrio foi projetado para uma luminÃria de 54 W e operando em alta frequÃncia (atà 165 kHz), possibilitando a reduÃÃo do volume do circuito. Os resultados experimentais obtidos do circuito MCD e MCC sÃo analisados e validam a proposta, mostrando que o conversor apresenta rendimento elevado

CoordenaÃÃo de AperfeÃoamento de Pessoal de NÃvel Superior / Este trabalho apresenta o estudo, o projeto e a implementaÃÃo de um driver trifÃsico para diodos emissores de luz (LEDs) baseado num conversor com capacitor chaveado (SC â Switched Capacitor), tambÃm conhecido como charge-pump. Uma luminÃria LED com a tecnologia Chip-on-Board (COB), que proporciona uma elevada densidade de potÃncia, à utilizada como carga. Assim como os LEDs, os drivers destes dispositivos devem apresentar uma longa vida Ãtil e um elevado rendimento. A vida Ãtil dos drivers para LEDs à geralmente limitada pelo uso de capacitores eletrolÃticos convencionais. Estes dispositivos apresentam uma vida Ãtil incompatÃvel com a dos LEDs e, por isso, nÃo devem ser utilizados nos seus drivers. AlÃm disso, os drivers para LEDs devem proporcionar uma baixa ondulaÃÃo de corrente nos LEDs, garantindo um baixo flicker percentual e evitando danos à saÃde humana. Diante destes problemas, o conversor trifÃsico SC proposto nÃo utiliza capacitores eletrolÃticos, o que eleva a expectativa de vida Ãtil do driver. O conversor emite um baixo flicker percentual e à capaz de estabilizar a corrente de saÃda sem a necessidade de um controle de malha fechada, o que pode reduzir os custos de projeto. A topologia permite a dimerizaÃÃo dos LEDs atravÃs da variaÃÃo da frequÃncia de comutaÃÃo. Resultados experimentais de um protÃtipo de 216 W sÃo analisados e discutidos para validaÃÃo da proposta. Em condiÃÃes nominais, o conversor apresentou um rendimento global de 91,5%, um fator de potÃncia acima de 0,99 e uma distorÃÃo harmÃnica menor que 5% nas trÃs fases, obedecendo as Classes A e C da norma IEC 61000-3-2:2014. AlÃm disso, foi obtida uma ondulaÃÃo de corrente de alta frequÃncia igual a 16,97% e um flicker percentual de 4,97%, estando de acordo com as recomendaÃÃes da IEEE. A dimerizaÃÃo dos LEDs permitiu a reduÃÃo da potÃncia de saÃda em atà 50%, com rendimento prÃximo a 91%, fator de potÃncia acima de 0,97, distorÃÃo harmÃnica total inferior a 6% para as trÃs fases e flicker percentual menor que 7% para toda a faixa de potÃncia. / This paper presents the study, design and implementation of a three-phase light-emitting diode (LED) driver based on a switched capacitor (SC) converter, also known as charge-pump. A LED lamp with Chip-On-Board (COB) technology, which provides a high power density, is used as load. As the LEDs, drivers of these devices must have a high efficiency and a long useful lifetime, which is usually limited by the use of conventional electrolytic capacitors. These devices have an incompatible lifetime with LEDs and, therefore, they should not be used in their drivers. In addition, the LED drivers should provide a low ripple current in LEDs, which can provide the emission of a low percent flicker. Studies demonstrate that excessive percent flicker may cause damage to human health. Given these problems, the proposed switched capacitor LED driver does not use electrolytic capacitors, which increases the expectative of useful lifetime of the driver. It emits a low percent flicker, which reduces the risks to human health. It can stabilize the output current without the need of a closed-loop control, which may reduce design costs. It allows the LEDs dimming by varying the switching frequency. An experimental prototype rated at 216 W has been developed in order to evaluate the performance of the proposed approach, while results are properly presented and discussed. In nominal conditions, the drive presented an overall efficiency of 91.5%, a power factor greater than 0.99 and a current total harmonic distortion lower than 5% in three phases. The harmonic currents are in accordance with the limits imposed by IEC Standard 61000-3-2:2014 to class A and C equipment. Furthermore, a high frequency current ripple equal to 16.97% and a percent flicker of 4.97% was obtained, which is in accordance with IEEE recommendations. The LEDs dimming allowed the reduction of the output power up to 50%, while the efficiency remained close to 91% and the power factor remained above 0.97. In addition, the total harmonic distortion was below 6% and the percent flicker was lower than 7% for the entire dimming range.