Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results.

CDMA channel selection requires sharp as well as wide-band Filtering. SAW Filters which have been used for this purpose are only available in IF range. In direct conversion receivers this has to be done at low frequencies. Switched Capacitor technique has been employed to design a low power, highly selective low-pass channel select Filter for CDMA wireless receivers. The topology which has been chosen ensures the low sensitivity of the Filter response. The circuit has been designed in a mixed-mode 0. 18u CMOS technology working with a single supply of 1. 8 V while its current consumption is less than 10 mA.

CDMA channel selection requires sharp as well as wide-band Filtering. SAW Filters which have been used for this purpose are only available in IF range. In direct conversion receivers this has to be done at low frequencies. Switched Capacitor technique has been employed to design a low power, highly selective low-pass channel select Filter for CDMA wireless receivers. The topology which has been chosen ensures the low sensitivity of the Filter response. The circuit has been designed in a mixed-mode 0. 18u CMOS technology working with a single supply of 1. 8 V while its current consumption is less than 10 mA.

abstract: The dissertation encompasses the transformer-less single phase PV inverters for both the string and microinverter applications. Two of the major challenge with such inverters include the presence of high-frequency common mode leakage current and double line frequency power decoupling with reliable capacitors without compromising converter power density. Two solutions are presented in this dissertation: half-bridge voltage swing (HBVS) and dynamic dc link (DDCL) inverters both of which completely eliminates the ground current through topological improvement. In addition, through active power decoupling technique, the capacitance requirement is reduced for both, thus achieving an all film-capacitor based solution with higher reliability. Also both the approaches are capable of supporting a wide range of power factor. Moreover, wide band-gap devices (both SiC and GaN) are used for implementing their hardware prototypes. It enables the switching frequency to be high without compromising on the converter efficiency. Also it allows a reduced magnetic component size, further enabling a high power density solution, with power density far beyond the state-of-the art solutions. Additionally, for the transformer-less microinverter application, another challenge is to achieve a very high gain DC-DC stage with a simultaneous high conversion efficiency. An extended duty ratio (EDR) boost converter which is a hybrid of switched capacitors and interleaved inductor technique, has been implemented for this purpose. It offers higher converter efficiency as most of the switches encounter lower voltage stress directly impacting switching loss; the input current being shared among all the interleaved converters (inherent sharing only in a limited duty ratio), the inductor conduction loss is reduced by a factor of the number of phases. Further, the EDR boost converter has been studied for both discontinuous conduction mode (DCM) operations and operations with wide input/output voltage range in continuous conduction mode (CCM). A current sharing between its interleaved input phases is studied in detail to show that inherent sharing is possible for only in a limited duty ratio span, and modification of the duty ratio scheme is proposed to ensure equal current sharing over all the operating range for 3 phase EDR boost. All the analysis are validated with experimental results. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Les nouveaux besoins en communications sans fil pussent le développement de systèmes de transmission RF en termes the reconfigurabilité, multistandard et à basse consommation. Ces travaux de thèse font l’objet de la proposition d’une nouvelle architecture de réception capable d’adresser ces aspects dans le contexte des réseaux WPAN. La technique de sous échantillonnage (BPS-Bandpass Sampling) est appliquée et permet d’exploiter et certain nombre d’avantages liées au traitement du signal à Temps Discret (DT-Discrete Time signal processing), notamment le filtrage et la décimation. Si comparées à la Radio Logicielle, ces techniques permettent de relâcher les contraintes liées aux ADCs en maintenant des caractéristiques multistandard et de reconfigurabilité. Un simulateur dans le domaine fréquentiel large bande a été développé sous MATLAB pour répondre à des limitations au niveau système comme par exemple le repliement spectral et le produit gain bande. En addition avec une nouvelle méthode de conception système, cet outil permet de séparer les différentes contraintes des blocs pour la définition d’un plan de fréquence et the filtrage optimaux. La séparation des différentes contributions dans la dégradation du SNDR (notamment le bruit thermique, bruit de phase, non linéarité et le repliement), permet de relâcher de spécifications critiques liées à la consommation de puissance. L’architecture à sous échantillonnage proposée dans la thèse est résultat d’une comparaison quantitative des différentes architectures à sous échantillonnage, tout en appliquant la méthode et l’outil de conception système développés. Des aspects comme l’optimisation du filtrage entre les techniques à temps continu et temps discret et le plan de fréquence associé, permettent de trouve l’architecture qui représente le meilleur compromis entre la consommation électrique et l’agilité, dans le contexte voulu. Le bloc de filtrage à temps discret est identifié comme étant critique, et une étude sur les limitations d’implémentation circuit est menée. Des effets come les capacités parasites, l’imparité entre les capacités, le bruit du commutateur, la non linéarité, le gain finit de Ampli OP, sont évalués à travers d’une simulation comportementale en VHDL-AMS. On observe la robustesse des circuits orientés temps discret par rapport les contraintes des nouvelles technologies intégrés. Finalement, le système est spécifié en termes de bruit de phase, qui peuvent représenter jusqu’à 30% de la consommation en puissance. Dans ce but, une nouvelle méthode numérique est proposée pour être capable d’évaluer le rapport signal sur distorsion due au jitter SDjR dans le processus de sous échantillonnage. En plus, une conclusion non intuitive est survenue de cette étude, où on que réduire la fréquence d’échantillonnage n’augmente pas les contraintes en termes de jitter pour le système. L’architecture proposée issue de cette étude est sujet d’un développement circuit pour la validation du concept. / New needs on wireless communications pushes the development in terms reconfigurable, multistandards and low power radio systems. The objective of this work is to propose and design new receiver architecture capable of addressing these aspects in the context of the WPAN networks. The technique of Bandpass Sampling (BPS) is applied and permits to exploit a certain number of advantages linked to the discrete time (DT) signal processing, notably filtering and decimation. Compared to the Software-defined Radio (SDR), these techniques permit to relax the ADC constraints while keeping the multi standard and reconfigurable features. A wide band system level simulation tool is developed using MATLAB platform to overcome system level limitations such spectral aliasing and gain bandwidth product. In addition to a new system design method, the tool helps separating the blocks constraints and defining the optimum frequency plan and filtering. Separating the different contributions on the SNDR degradation (noise, phase noise, non linearity, and aliasing), critical specifications for power consumption can be relaxed. The proposed BPS architecture on the thesis is a result of a quantitative comparison of different BPS architectures, applying the system design method and tool. Aspects such filtering optimization between continuous and discrete time filtering and the associated frequency plan permitted to find the architecture which represents the best trade-off between power consumption and agility on the aimed context. The DT filtering block is therefore identified as critical block, which a study on the circuit implementation limitations is carried out. Effects such parasitic capacitances and capacitance mismatch, switch noise, non linear distortion, finite gain OTA, are evaluated through VHDL-AMS modelling. It is observed the robustness of discrete time oriented circuits. Finally, phase noise specifications are given considering that frequency synthesis circuits may represent up to 30% of the power consumption. For that goal, a new numerical method is proposed, capable of evaluating the signal to jitter distortion ratio SDjR on the BPS process. Moreover, a non intuitive conclusion is given, where reducing the sampling frequency does not increase the constraints in terms of jitter. The proposed architecture issue from this study is in stage of circuit level design in the project team of LETI for final proof of concept.

Les appareils multimédias portables nécessitent toujours plus d'innovation pour satisfaire les besoins des utilisateurs. Les fabricants de système-sur-puces font donc face à une forte demande en capacité de calcul jusqu'à lors réservée aux ordinateurs de bureau. Ce transfert de performance se répercute inévitablement sur la consommation de ces appareils alors que dans le même temps la capacité des batteries n'est pas en mesure de répondre à cet accroissement. De nombreux compléments matériels et logiciels sont mis en places afin d'économiser l'énergie au maximum sans toutefois dégrader les performances. La modulation de la fréquence de fonctionnement et de la tension d'alimentation est certainement la plus efficace mais reste néanmoins limitée par les coûts et les contraintes d'encombrement exigées par la taille des appareils. La réponse à un tel problème passe nécessairement par l'intégration d'une partie de l'alimentation dans la puce. La conversion DC-DC basée sur des convertisseurs à capacités commutées est prometteuse car elle permet de garder un maximum de compatibilité avec les process CMOS actuels. Cette thèse explore donc la conception d'une architecture d'alimentation utilisant des convertisseurs à capacités commutées. Un étage de puissance avec une tension d'entrée est de 1.8 V et des ratios programmables permet d'obtenir le rendement maximum pour une plage de tension de sortie allant de 0.3 à 1.2 V. La tension de sortie peut varier en fonction du point de fonctionnement requit par le système. Afin d'assurer le maximum de compatibilité avec la conception du circuit numérique à alimenter, une architecture modulaire basée sur les capacités MIM est privilégiée. Les capacités sont placées au dessus de la fonction numériques et les interrupteurs de puissance sont insérés à sa périphérie. Cette architecture permet également d'entrelacer les cellules de conversion afin de réduire l'ondulation de la tension de sortie. La fréquence de commutation du convertisseurs est communément utilisée pour réguler la tension de sortie et des stratégies de contrôles linéaires et non linéaires sont donc explorées. Un prototype de convertisseur présentant une densité de puissance de 310mW/mm2 pour un rendement de 72.5% a été fabriqué dans la technologie 28nm FDSOI de STMicroelectronics. La surface requise pour le convertisseur nécessite que 11.5% de la surface du circuit à alimenter. La méthodologie de conception du convertisseur a finalement été appliquée à un régulateur de tension dans le domaine négatif pour des applications de polarisation de caisson à basse consommation. / Mobile and multimedia devices offer more innovations and enhancements to satisfy user requirements. Chip manufacturers thus propose high performances SoC to address these needs. Unfortunately the growth in digital resources inevitably increases the power consumption while battery life-time does not rise as fast. Aggressive power management techniques such as dynamic voltage and frequency scaling have been introduced in order to keep competitive and relevant solutions. Nonetheless continuing in this direction involves more disruptive solutions to meet space and cost constraints. Fully integrated power supply is a promising solution. Switched-capacitor DC-DC converters seem to be a suitable candidate to keep compatibility with the manufacturing process of digital SoCs. This thesis focuses on the design of an embedded power supply architecture using switched-capacitor DC-DC converters.Addressing a large range of output power with significant efficiency leads to consider a multi-ratio power stage. With respect to the typical digital SoC, the input voltage is 1.8 V and the converter is specified to deliver an output voltage in the 0.3-1.2 V range. The reference voltage is varying according to typical DVFS requirements. A modular architecture accommodates the digital design flow where the flying capacitors are situated above the digital block to supply and the power switches are located as an external ring. Such an architecture offers high flexibility. Interleaving strategy is considered to mitigate the output voltage ripple. Such a converter admits the switching frequency as a control variable and linear regulation and hysteretic control are analyzed. A prototype has been fabricated in 28nm FDSOI technology by STMicroelectronics. A power density of 310 mW/mm2 is achieved at 72.5% peak efficiency with a silicon area penalty of 11.5% of the digital block area. The successful design methodology has been also applied to the design of a negative SC converter for body-biasing purpose in FDSOI. Simulation results demonstrate a strong interest for low power application.

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A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification. / Graduation date: 2012 / Access restricted to the OSU Community, at author's request, from July 19, 2012 - July 19, 2013

Based on different sampling theorem, for example classic Shannon’s sampling theorem and Papoulis’ generalized sampling theorem, signals are processed by the sampling devices without loss of information. As an interface between radio receiver front-ends and digital signal processing blocks, sampling devices play a dominant role in digital radio communications. Under the concept of Software Defined Radio (SDR), radio systems are going through the second evolution that mixes analog, digital and software technologies in modern radio designs. One design goal of SDR is to put the A/D converter as close as possible to the antenna. BandPass Sampling (BPS) enables one to have an interface between the RF or the higher IF signal and the A/D converter, and it might be a solution to SDR. However, three sources of performance degradation present in BPS systems, harmful signal spectral overlapping, noise aliasing and sampling timing jitter, hinder the conventional BPS theory from practical circuit implementations. In this thesis work, Generalized Quadrature BandPass Sampling (GQBPS) is first invented and comprehensively studied with focus on the noise aliasing problem. GQBPS consists of both BPS and FIR filtering that can use either real or complex coefficients. By well-designed FIR filtering, GQBPS can also perform frequency down-conversion in addition to noise aliasing reduction. GQBPS is a nonuniform sampling method in most cases. With respect to real circuit implementations, uniform sampling is easier to be realized compared to nonuniform sampling. GQBPS has been also extended to Generalized Uniform BandPass Sampling (GUBPS). GUBPS shares the same property of noise aliasing suppression as GQBPS besides that the samples are uniformly spaced. Due to the moving average operation of FIR filtering, the effect of sampling jitter is also reduced to a certain degree in GQBPS and GUBPS. By choosing a suitable sampling rate, harmful signal spectral overlapping can be avoided. Due to the property of quadrature sampling, the “self image” problem caused by I/Q mismatches is eliminated. Comprehensive theoretical analyses and program simulations on GQBPS and GUBPS have been done based on a general mathematic model. Circuit architecture to implementing GUBPS in Switched-Capacitor circuit technique has been proposed and analyzed. To improve the selectivity at the sampling output, FIR filtering is extended by adding a 1st order complex IIR filter in the implementation. GQBPS and GUBPS operate in voltage-mode. Besides voltage sampling, BPS can also be realized by charge sampling in current-mode. Most other research groups in this area are focusing on bandpass charge sampling. However, the theoretical analysis shows that our GQBPS and GUBPS in voltage mode are more efficient to suppress noise aliasing as compared to bandpass charge sampling with embedded filtering. The aliasing bands of sampled-data spectrum are always weighted by continuous-frequency factors for bandpass charge sampling with embedded filtering while discrete-frequency factors for GQBPS and GUBPS. The transmission zeros of intrinsic filtering will eliminate the corresponding whole aliasing bands of both signal and noise in GQBPS and GUBPS, while it will only cause notches at a limited set of frequencies in bandpass charge sampling. In addition, charge sampling performs an intrinsic continuous-time sinc function that always includes lowpass filtering. This is a drawback for a bandpass input signal. / QC 20100921