Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第16855号 / 工博第3576号 / 新制||工||1540(附属図書館) / 29530 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 引原 隆士, 教授 木本 恒暢, 教授 小野寺 秀俊 / 学位規則第4条第1項該当

With the advancement of semiconductor technology, the System on Chip (SoC) is becoming more and more complex, so the on-chip communication has become a bottleneck of SoC Design. Since the traditional bus system is inefficient and not scalable, the Network-On-Chip (NoC) has emerged as the promising communication mechanism for complex SoCs. As some systems have specific performance requirements, such as a minimum throughput (for real-time streaming data) or bounded latency (for interrupts, process synchronization, etc), communication with Guaranteed Service (GS) support becomes crucial for predictable SoC architectures. Circuit Switching (CS) is a popular approach to support GS, which firstly has to allocate an exclusively connection (circuit) between the source and destination nodes, and then the data packets are delivered over this connection. However, it is inefficient and inflexible because the resource is occupied by single connection during its whole lifetime, which can block other communications. Hence, two extensions of CS have been proposed to share resources: i) Time-Division Multiplexing (TDM), in which the available link capacity is split into multiple time slots to be shared by different flows in TDM scheme; and ii) Space-Division-Multiplexing (SDM), in which only a subset (sub-channel) of the link wires is exclusively allocated to a specific connection, while the remaining wires of the link can be used by other flows. The connection allocation is critical for CS, since the data delivery can start only after the associated connection is allocated. In this thesis, we propose a dedicated hardware connection allocator to solve the dynamic connection allocation problem for CS NoCs, which has to i) allocate a contention-free path between source-destination pairs and ii) allocate appropriate portions of link bandwidth (appropriate number of time slots and subsets) along the path. The dedicated connection allocator, called NoCManager, solves the connection allocation problem by employing a trellis-search based shortest path algorithm. The trellis search can explore all possible paths between source node and destination. Moreover, it shall find the requested path in a fixed low latency and can guarantee the path optimality in terms of path length if the path is available. In this thesis, two different trellis graphs, Forward-Backtrack trellis and Register-Exchange trellis are proposed. The Forward-Backtrack trellis completes the path search in two steps: forward search and backtracking. Firstly, the forward search begins at source node that traverses the network to find the free path. When destination node is reached, the backtrack starts from destination to select the survivor path and collect the associated path parameters. However, Register-Exchange trellis saves the entire survivor path sequences during forward search. Consequently, the backtracking step can be omitted, and thus the allocation time is halved compared to forward-backtrack approaches. Moreover, each trellis graph consists of three categories, unfolded structure, folded structure and bidirectional structure. The unfolded structure can provide high allocation speed while folded structure is more efficient from a hardware point of view. The bidirectional structure starts the search at two sides, source node and destination node simultaneously, so the allocation speed is 2 times faster than previous unidirectional search. Furthermore, in order to address the scalability issue of previous centralized systems, the partitioned architecture (i.e. spatial partitioning technique) is proposed to divide the large system into multiple smaller differentiated logical partitions served by local NoCManagers. This partitioning technique keeps the request load of the manager and manager-node communication overhead moderate. Inside each partition, the path search problem is solved by a local manager with trellis-search algorithm. To establish a path that crosses partitions, the managers communicate with each other in distributed manner to converge the global path. In order to further enhance the path diversity and resource utilization, we adopt the combined TDM and SDM technique. In combined TDM-SDM approach, each SDM sub-channel is split into multiple time slots so that can be shared by multiple flows. Hence, the number of sub-channels can be kept moderate to reduce router complexity, while still providing higher path diversity than TDM scheme. In order to investigate and optimize TDM-SDM partitioning strategy, we studied the influence of different TDM-SDM link partitioning strategies on success rate and path length that allowed us to find the optimal solution. The dedicated connection allocator using the trellis-search algorithm is employed for TDM, SDM and TDM-SDM CS. In the end, we present the router architecture that combines the circuit-switching network (for GS communication) and packet-switching network (for best-effort communication).

This thesis contains detailed study of a newly discovered effect of quench switch- ing in thin films of antiferromagnetic CuMnAs. This effect can be used to induce highly reproducible resistance switching behaviour in response to electrical or optical laser pulsing. The resistance changes reach up to GMR-like values of 20 % at room temperature and 100 % at low temperatures. We attribute these changes to the nano-fragmentation of magnetic domain structure. After CuMnAs is pulsed into a high resistance state, a characteristic period of time follows, during which the resistance relaxes back to the original value. This relaxation can be described by Kohlrausch stretched exponential function. This type of relaxation is characteristic for behaviour of correlated complex systems, which goes well with the idea of highly fragmented and correlated magnetic states of quenched CuMnAs. The quench switching effect is studied in detail on devices with different geometries, for various parameters of the writing pulse, as well as growth pa- rameters of the CuMnAs films. The switching is demonstrated in CuMnAs films prepared on GaP, GaAs and Si substrates, where the quality of the film differs. This illustrates robustness and application potential of the effect. 1

Mes travaux de thèse dans les laboratoires SATIE de ENS de Cachan et Ampère de l’INSA de Lyon se sont déroulés dans le cadre du projet Gestion OptiMisée de l'Energie (GENOME) pour étudier le potentiel de certains composants de puissance (JFET, MOSFET et BJT) en carbure de silicium (SiC) dans des convertisseurs électroniques de puissance dédiés à des applications aéronautiques suite au développement de l'avion plus électrique. La première partie de mes travaux étudie la robustesse de MOSFET et BJT en SiC soumis à des régimes de court circuit. Pour les MSOFET SiC, en soumettant ces transistors à la répétition de plusieurs courts-circuits, nous observons une évolution du courant de fuite de grille qui semble être un bon indicateur de vieillissement. Nous définissons une énergie critique répétitive pour évaluer la robustesse à la répétition de plusieurs courts-circuits. Aucun effet significatif de la température ambiante n’a pu être mis en évidence sur la robustesse des MOSFET et BJT SiC sous contraintes de court-circuit. Pour les MOSFET, nous avons également constaté une élévation significative du courant de fuite de grille en augmentant de 600V à 750V la tension, ce qui se traduit également par une défaillance plus rapide. Après ouverture des boîtiers des MOSFET Rohm ayant présenté un court-circuit entre grille et source après défaillance, on remarque une fusion de la métallisation de source qui vient effectivement court-circuiter grille et source. Dans ce mode de défaillance particulier, le court-circuit entre grille et source auto-protège la puce en lui permettant de s’ouvrir.La deuxième partie de ce mémoire est consacrée à l’étude de JFET, MSOFET et BJT SiC en régime d’avalanche. Les JFET de SemiSouth et les BJT de Fairchild présentent une bonne robustesse à l’avalanche. Mais le test d'avalanche révèle la fragilité du MOSFET Rohm puisqu’il entre en défaillance avant d’entrer en régime d’avalanche. La défaillance du MOSFET Rohm et sa faible robustesse en régime d’avalanche sont liées à l’activation du transistor bipolaire parasite. Le courant d'avalanche n’est qu’une très faible partie du courant dans l’inductance et circule du drain/collecteur à la grille/base pour maintenir le transistor en régime linéaire. Une résistance de grille de forte valeur diminue efficacement le courant d'avalanche à travers la jonction drain-grille pour le JFET.La troisième partie concerne l’étude de la commutation de BJT SiC à très haute fréquence de découpage. Nous avons dans un premier temps cherché à valider des mesures de pertes par commutation. Après avoir vérifié l'exactitude de la méthode électrique par rapport à une méthode calorimétrique simplifiée, nous montrons que la méthode électrique est adaptée à l’estimation des pertes de commutation mais nécessite beaucoup d’attention. En raison de mobilité élevée des porteurs de charge dans le SiC, nous montrons que le BJT SiC ne nécessite pas l’utilisation de diode d’anti-saturation. Enfin, aucune variation significative des pertes de commutation n’a pu être constatée sur une plage de température ambiante variant de 25°C à 200°C.La quatrième partie concentre l’étude du comportement de MOSFET SiC sous contraintes HTRB (High Temperature Reverse Bias) et dans une application diode-less dans laquelle les transistors conduisent un courant inverse à travers le canal, exception faite de la phase de temps mort pendant laquelle c’est la diode de structure qui assurera la continuité du courant dans la charge. Les résultats montrent que la diode interne ne présente aucune dégradation significative lors de la conduction inverse des MOSFET. Le MOSFET Cree testé montre une dérive de la tension de seuil et une dégradation de l’oxyde de grille qui sont plus significatives lors des essais dans l’application diode-less que sous des tests HTRB. La dérive de la tension de seuil est probablement due au champ électrique intense régnant dans l’oxyde et aux pièges de charge dans l'oxyde de grille. / My PhD work in laboratories SATIE of ENS de Cachan and Ampère of INSA de Lyon is a part of project GEstioN OptiMisée de l’Energie (GENOME) to investigate the potential of some Silicon carbide (SiC) power devices (JFET, MOSFET and BJT) in power electronic converters dedicated to aeronautical applications for the development of more electric aircraft.The first part of my work investigates the robustness of MOSFET and SiC BJT subjected to short circuit. For SiC MOSFETs, under repetition of short-term short circuit, a gate leakage current seems to be an indicator of aging. We define repetitive critical energy to evaluate the robustness for repetition of short circuit. The effect of room temperature on the robustness of SiC MOSFET and BJT under short circuit stress is not evident. The capability of short circuit is not improved by reducing gate leakage current for MOSFET, while BJT shows a better robustness by limiting base current. For MSOFET, a significant increase in gate leakage current accelerates failure for DC voltage from 600V to 750V. After opening Rohm MOSFETs with a short circuit between gate and source after failure, the fusion of metallization is considered as the raison of failure. In this particular mode of failure, the short circuit between gate and source self-protects the chip and opens drain short current.The second part of the thesis is devoted to the study of SiC JFET, MSOFET and BJT in avalanche mode. The SemiSouth JFET and Fairchild BJT exhibit excellent robustness in the avalanche. On the contrary, the avalanche test reveals the fragility of Rohm MOSFET since it failed before entering avalanche mode. The failure of Rohm MOSFET and its low robustness in avalanche mode are related to the activation of parasitic bipolar transistor. The avalanche current is a very small part of the current in the inductor. It flows from the drain/collector to the gate/base to drive the transistor in linear mode. A high-value gate resistance effectively reduces the avalanche current through the drain-gate junction to the JFET.The third part of this thesis concerns the study of switching performance of SiC BJT at high switching frequency. We initially attempted to validate the switching loss measurements. After checking the accuracy of the electrical measurement compared to calorimetric measurement, electrical measurement is adopted for switching power losses but requires a lot of attention. Thanks to high carrier charge mobility of SiC material, SiC BJT does not require the use of anti-saturation diode. Finally, no significant variation in switching losses is observed over an ambient temperature range from 25°C to 200°C.The fourth part focuses on the study of SiC MOSFET behavior under HTB (High Temperature Reverse Bias) and in diode-less application in which the transistors conduct a reverse current through the channel, except for the dead time during which the body diode ensure the continuity of the current in the load. The results show that the body diode has no significant degradation when the reverse conduction of the MOSFET. Cree MOSFET under test shows a drift of the threshold voltage and a degradation of the gate oxide which are more significant during the tests in the diode-less application than under HTRB test. The drift of the threshold voltage is probably due to intense electric field in the oxide and the charge traps in the gate oxide.

This thesis is focused on a detailed investigation of the optically induced quench switching effect in different films of antiferromagnetic CuMnAs. The quench switching effect was recently discovered to be highly reproducible resistance switch- ing, which can be excited by electrical and optical laser pulses. This thesis com- pares the amplitude response to laser-induced quench switching for samples on the different substrate material, samples with different stoichiometries, and sam- ples with different thicknesses of CuMnAs film. The effects of different ratios between the laser spot and the size of the measured device are investigated, and position-dependent measurements are also presented. It is shown that resistivity change with optical excitation using a single 120 femtosecond laser pulse can, in ideal conditions, reach up to 15% at room temperature, which is comparable with the maximum signal obtained with electrical pulses. All of the measure- ments combined with current knowledge of quench switching illustrate the robust behavior of this mechanism across a wide range of conditions. 1

京都大学 / 0048 / 新制・課程博士 / 博士(経済学) / 甲第19953号 / 経博第540号 / 新制||経||279(附属図書館) / 33049 / 京都大学大学院経済学研究科経済学専攻 / (主査)教授 江上 雅彦, 教授 若井 克俊, 教授 原 千秋 / 学位規則第4条第1項該当 / Doctor of Economics / Kyoto University / DFAM

Indiana University-Purdue University Indianapolis (IUPUI) / An Adaptive Cruise Control (ACC) system is a driver assistance system that assists a driver to improve driving safety and driving comfort. The design of ACC controller often involves the design of a switching logic that decides where and when to switch between the two modes in order to ameliorate driving comfort, mitigate the chance of a potential collision with the preceding vehicle while reduce long-distance driving load from the driver. In this thesis, a new strategy for designing ACC controller is proposed. The proposed control strategy utilizes Range vs. Range-rate chart to illustrate the relationship between headway distance and velocity difference, and then find out a constant deceleration trajectory on the chart, which the following vehicle is controlled to follow. This control strategy has a shorter elapsed time than existing ones while still maintaining a relatively safe distance during transient process. String stability issue has been addressed by many researchers after the adaptive cruise control (ACC) concept was developed. The main problem is when many vehicles with ACC controller forming a vehicle platoon end to end, how the control algorithm is designed to ensure that the spacing error, which is the deviation of the actual range from the desired headway distance, would not amplify as the number of following vehicles increases downstream along the platoon. In this thesis, string stability issues have been taken into consideration and constraints of parameters of an ACC controller are derived to mitigate steady state error propagation.

In the field of power electronics there is always a push to create smaller and more efficient power conversion systems. This push is driven by the industry that uses the power systems, and can be realized by new semiconductor devices or new techniques. This examination describes a novel technique for a small and highly efficient method of converting relatively high DC voltage to a very low voltage for use in the telecommunications industry. A modification to the standard Forward Resonant converter results in improvements in component stress, system efficiency, response time, and control circuitry. This examination describes background information needed to understand the concepts in DC to DC power systems, "soft-switching" topologies, and control methods for these systems. The examination introduces several topologies that are currently being used, and several types that have been previously analyzed, as a starting point for the detailed analysis of the proposed converter topology. A detailed analytical analysis is given of the proposed topology, including secondary effects, and component stresses. This analysis is compared to the results found from both Pspice simulation, and a working DC to DC converter. Finally, the topology is examined for potential improvements, and possible refinements to the model described.

Optical networking, employing wavelength division multiplexing (WDM), is seen as the technology of the future for the Internet. This dissertation investigates several important problems affecting optical circuit switching (OCS) and optical burst switching (OBS) networks. Novel algorithms and new approaches to improve the performance of these networks through effective routing and channel scheduling are presented. Extensive simulations and analytical modeling have both been used to evaluate the effectiveness of the proposed algorithms in achieving lower blocking probability, better fairness as well as faster switching. The simulation tests were performed over a variety of optical network topologies including the ring and mesh topologies, the U.S. Long-Haul topology, the Abilene high-speed optical network used in Internet 2, the Toronto Metropolitan topology and the European Optical topology. Optical routing protocols previously published in the literature have largely ignored the noise and timing jitter accumulation caused by cascading several wavelength conversions along the lightpath of the data burst. This dissertation has identified and evaluated a new constraint, called the wavelength conversion cascading constraint. According to this constraint, the deployment of wavelength converters in future optical networks will be constrained by a bound on the number of wavelength conversions that a signal can go through when it is switched all-optically from the source to the destination. Extensive simulation results have conclusively demonstrated that the presence of this constraint causes significant performance deterioration in existing routing and wavelength assignment (RWA) algorithms. Higher blocking probability and/or worse fairness have been observed for existing RWA algorithms when the cascading constraint is not ignored. To counteract the negative side effect of the cascading constraint, two constraint-aware routing algorithms are proposed for OCS networks: the desirable greedy algorithm and the weighted adaptive algorithm. The two algorithms perform source routing using link connectivity and the global state information of each wavelength. Extensive comparative simulation results have illustrated that by limiting the negative cascading impact to the minimum extent practicable, the proposed approaches can dramatically decrease the blocking probability for a variety of optical network topologies. The dissertation has developed a suite of three fairness-improving adaptive routing algorithms in OBS networks. The adaptive routing schemes consider the transient link congestion at the moment when bursts arrive and use this information to reduce the overall burst loss probability. The proposed schemes also resolve the intrinsic unfairness defect of existing popular signaling protocols. The extensive simulation results have shown that the proposed schemes generally outperform the popular shortest path routing algorithm and the improvement could be substantial. A two-dimensional Markov chain analytical model has also been developed and used to analyze the burst loss probabilities for symmetrical ring networks. The accuracy of the model has been validated by simulation. Effective proactive routing and preemptive channel scheduling have also been proposed to address the conversion cascading constraint in OBS environments. The proactive routing adapts the fairness-improving adaptive routing mentioned earlier to the environment of cascaded wavelength conversions. On the other hand, the preemptive channel scheduling approach uses a dynamic priority for each burst based on the constraint threshold and the current number of performed wavelength conversions. Empirical results have proved that when the cascading constraint is present, both approaches would not only decrease the burst loss rates greatly, but also improve the transmission fairness among bursts with different hop counts to a large extent.

ABSTRACT Digitally-Controlled Two-Phase Zero-Voltage-Switching Quasi-Resonant Buck Converter Brian Luc This thesis entails the design, construction, and performance analysis of a digitally-controlled two-phase Zero-Voltage Switching Quasi-Resonant (ZVS-QR) buck converter. The converter is aimed to address the issues associated with powering CPUs operating at lower voltage and high current. To evaluate its performance, the Two-Phase ZVS-QR buck converter is compared against a traditional Two-Phase buck converter. The design procedure required to implement both converters through utilizing the characterization curve and formulas derived from their circuit configurations will be presented. Computer simulation of the Two-Phase ZVS-QR buck converter is provided to exhibit its operation and potential for use in low voltage and high current applications. In addition, hardware prototypes for both ZVS-QR and traditional buck converters are constructed utilizing a Programmable Interface Controller (PIC). Results from hardware tests demonstrate the success of using digital controller for the 60W 12VDC to 1.5VDC ZVS-QR buck converter. Merits and drawbacks based on the operation and performance of both converters will also be assessed and described. Further work to improve the performance of ZVS-QR will also be presented. Keywords: Buck Converter; Zero-Voltage-Switching; Multi-Phase; Efficiency; Switching Loss