Thesis (Ph.D)--Stanford University, 1999. / Title from PDF t.p. (viewed May 9, 2002). "August 1999." "Adminitrivia V1/Prg/19990826"--Metadata.

Interfacing and operating AC power electronic systems requires rapid and accurate estimation of the phase angle of the power source, and specifically of the positive sequence of the three-phase utility grid voltage. This is needed to ensure reliable operation of the power control devices and of the resulting power flow. However, the quality of this information is undermined by various distortions and unbalanced conditions of the three-phase grid voltage. Phase estimation and power control can both be performed in real time by a DSP, but a DSP typically has limited computational resources, especially in regards to speed and memory, which motivates the search for computationally efficient algorithms to accomplish these tasks. In contrast to conventional PLL techniques, recent approaches have used adaptive amplitude estimation to enhance the acquisition of the phase information, resulting in faster response and improved performance. This thesis presents a novel technique to estimate the phase of the positive sequence of a three-phase voltage in the presence of frequency variations and unbalanced conditions, referred to as hybrid negative sequence adaptive synchronous amplitude estimation with PLL, or H-NSASAE-PLL. The key feature consists of a feedback structure which embeds a positive sequence PLL and an adaptive synchronous negative sequence estimator to enhance the performance of the PLL. The resulting benefits include faster estimation of the phase of the positive sequence under unbalanced conditions with zero steady state error, simplified tuning of PLL parameters to address a wide range of application requirements, robust performance with respect to distortions and PLL parameters, a structure of minimal dynamical order (fifth) to estimate the main signal parameters of interest, simplified discretization, and reduced computational costs, making the proposed technique suitable for real time execution on a DSP. The H-NSASAE-PLL is developed in the Matlab/Simulink environment, and a specialized test signal generator is developed to evaluate its performance. The overall system is executed, and experimental results are produced, in real time, on a dSPACE DS1104 controller board. / Power Engineering and Power electronics

Objectives were to: 1) Evaluate the effectiveness of presynchronization with GnRH before the CO‐Synch + CIDR protocol with timed AI (TAI) at 66 h in Bos indicus‐influenced cattle; 2) Characterize ovarian events associated with the presynchronization; 3) Evaluate the efficacy of measuring vaginal electrical resistance (VER) to assess follicular maturity at TAI; and 4) Compare serum concentrations of progesterone (P4) in ovariectomized cows bearing new or previously used CIDR devices with or without autoclaving. In Exp. 1 and 2, cattle received either GnRH or saline on day ‐7. The CO‐Synch + CIDR protocol included a CIDR insert and GnRH (GnRH‐1; day 0), removal of CIDR and PGF2α on day 7, and GnRH (GnRH‐2) and TAI 66 h after CIDR removal. In Exp. 1, pregnancy rate of females with BCS ≥ 5 tended to differ (P=0.085) between Presynch (38%) and CO‐Synch + CIDR (54%). In Exp. 2, ovulatory response to GnRH‐1 was greater (P<0.01) in the Presynchronization (58%) than in the CO‐Synch + CIDR (27.1%) group. Emergence of a follicular wave after GnRH‐1 and ovulation rate after GnRH‐2 did not differ between groups. More (P<0.01) females that developed a follicular wave after GnRH‐1 ovulated (82%) after GnRH‐2, compared to those that did not (29%). Mean VER (ohms) was greatest (101.4±0.8) on day 0 and declined (P<0.01) to 95.2±0.8 and 82±0.8, respectively, on days 7 and 10. We observed a low negative but significant relationship (r=0.38; P<0.001) between VER and follicular size on day 0, 7, and 10. VER difference (day 10 minus day 7) did not differ between females with small and large follicles at TAI. Mean concentrations of P4 during the 7‐day insertion period were greater (P<0.03) for new (3.7 ng/ml) and re‐used autoclaved (3.4 ng/ml) than for re‐used disinfected CIDRs (2.8 ng/ml). In summary, Presynch improved ovulation rate after GnRH‐1, but did not improve pregnancy rates compared to CO‐Synch + CIDR. Follicular maturity estimation was not feasible using VER as applied in this study. Autoclaving may be the best option when re‐using CIDR inserts because it creates greater concentrations of P4 during the first 48 h.

Pulse synchronization is the evolution of spontaneous firing action across a network of sensor nodes. In the pulse synchronization model all nodes across a network produce a pulse, or "fire", at regular intervals even without access to a shared global time. Previous researchers have proposed the Reachback Firefly algorithm for pulse synchronization, in which nodes react to the firings of other nodes by changing their period. We propose an extension to this algorithm for tolerating arbitrary or Byzantine faults of nodes. Our algorithm queues up all the firings heard in the current cycle and discards outliers at the end of the cycle. An adjustment is computed with the remaining values and used as a starting point of the next cycle. Through simulation we validate the performance of our algorithm and study the overhead in terms of convergence time and periodicity. The simulation considers two specific kinds of Byzantine faults, the No Jump model where faulty nodes follow their own firing cycle without reacting to firings heard from other nodes and the Random Jump model where faulty nodes fire at any random time in their cycle.

Objectives were to determine: 1) whether estradiol benzoate (EB) provides a superior alternative to GnRH for synchronizing emergence, growth and maturation of a new follicular wave for fixed timed AI (TAI) in Bos indicus-influenced cattle using CIDR-based protocols, 2) the effect of 48 h calf removal at CIDR removal on the rate of maturational synchrony of the dominant follicle and 3) the effect of varying the magnitude of peak plasma progesterone (P4) concentrations following CIDR insertion on the suppression of FSH and LH secretion in a CIDR-based protocol using EB. In experiment 1, sixty-four Braford (F-1) females were stratified by BCS, parity and days postpartum and assigned randomly to one of four groups in a 2 x 2 factorial arrangement of treatments: 1) Select-Synch + CIDR, 2) Select-Synch + CIDR with 48 h calf removal, 3) E-Synch + CIDR or 4) E-Synch + CIDR with 48 h calf removal. A greater number of cattle in the EB treated group exhibited NFWE compared to the GnRH group, 29 vs 17 cows for EB and GnRH respectively, (P<0.0006). Intervals to NFWE were also greater in EB treated cattle than in GnRH treated cattle, 4.2 vs 2.7 d for EB and GnRH treated cattle respectively, (P<0.0001). Proportions of GnRH- and EB-treated cows ovulating after CIDR removal did not differ. Post-CIDR suckling status did not affect ovulation frequency or interval to ovulation. In experiment 2, eight pubertal (F-1) heifers were used in a Latin Square design with four treatment levels of P4: 1) EB only, 2) EB and new CIDR, 3) EB and new autoclaved CIDR, 4) EB, new autoclaved CIDR and P4 injection at CIDR insertion. Treatments 2 through 4 increased (P < 0.01) mean plasma P4 concentrations compared to treatment 1, with treatment 4 creating the greatest increase in P4 with the longest duration. Suppression of plasma FSH was greatest in group 4 (P<0.08), with mean 60 h concentrations less than in all other groups. Mean concentrations of LH were lesser in group 4 than groups 1 and 2. Frequencies of occurrence of NFWE and ovulation and intervals to NFWE did not differ among treatments. Results indicate that the use of EB and CIDR to synchronize Brahman x Hereford females may provide better synchronization for TAI compared to GnRH and CIDR based protocols.

In this dissertation, we study two new approaches to fault detection for autonomous robots. The first approach involves the synthesis of software components that give a robot the capacity to detect faults which occur in itself. Our hypothesis is that hardware faults change the flow of sensory data and the actions performed by the control program. By detecting these changes, the presence of faults can be inferred. In order to test our hypothesis, we collect data in three different tasks performed by real robots. During a number of training runs, we record sensory data from the robots both while they are operating normally and after a fault has been injected. We use back-propagation neural networks to synthesize fault detection components based on the data collected in the training runs. We evaluate the performance of the trained fault detectors in terms of the number of false positives and the time it takes to detect a fault. The results show that good fault detectors can be obtained. We extend the set of possible faults and go on to show that a single fault detector can be trained to detect several faults in both a robot's sensors and actuators. We show that fault detectors can be synthesized that are robust to variations in the task. Finally, we show how a fault detector can be trained to allow one robot to detect faults that occur in another robot. The second approach involves the use of firefly-inspired synchronization to allow the presence of faulty robots to be determined by other non-faulty robots in a swarm robotic system. We take inspiration from the synchronized flashing behavior observed in some species of fireflies. Each robot flashes by lighting up its on-board red LEDs and neighboring robots are driven to flash in synchrony. The robots always interpret the absence of flashing by a particular robot as an indication that the robot has a fault. A faulty robot can stop flashing periodically for one of two reasons. The fault itself can render the robot unable to flash periodically. Alternatively, the faulty robot might be able to detect the fault itself using endogenous fault detection and decide to stop flashing. Thus, catastrophic faults in a robot can be directly detected by its peers, while the presence of less serious faults can be detected by the faulty robot itself, and actively communicated to neighboring robots. We explore the performance of the proposed algorithm both on a real world swarm robotic system and in simulation. We show that failed robots are detected correctly and in a timely manner, and we show that a system composed of robots with simulated self-repair capabilities can survive relatively high failure rates. We conclude that i) fault injection and learning can give robots the capacity to detect faults that occur in themselves, and that ii) firefly-inspired synchronization can enable robots in a swarm robotic system to detect and communicate faults.

Three-Phase Voltage Source Converters (VSCs) are finding widespread applications in grid integrated power conversion systems. The control systems of such VSCs are in an increasing number of these applications required to operate during voltage disturbances and unbalanced conditions. Control systems designed for grid side voltagesensor- less operation are at the same time becoming attractive due to the continuous drive for cost reduction and increased reliability of VSCs, but are not commonly applied for operation during unbalanced conditions. Methods for voltage-sensor-less grid synchronization and control of VSCs under unbalanced grid voltage conditions will therefore be the main focus of this Thesis. Estimation methods based on the concept of Virtual Flux, considering the integral of the converter voltage in analogy to the flux of an electric machine, are among the simplest and most well known techniques for achieving voltage-sensor-less grid synchronization. Most of the established techniques for Virtual Flux estimation are, however, either sensitive to grid frequency variations or they are not easily adaptable for operation under unbalanced grid voltage conditions. This Thesis addresses both these issues by proposing a simple approach for Virtual Flux estimation by utilizing a frequency-adaptive filter based on a Second Order Generalized Integrator (SOGI). The proposed approach can be used to achieve on-line frequency-adaptive varieties of conventional strategies for Virtual Flux estimation. The main advantage is, however, that the SOGI-based Virtual Flux estimation can be arranged in a structure that achieves inherent symmetrical component sequence separation under unbalanced conditions. The proposed method for Virtual Flux estimation can be used as a general basis for voltage-sensor-less grid synchronization and control during unbalanced conditions. In this Thesis, the estimated Virtual Flux signals are used to develop a flexible strategy for control of active and reactive power flow, formulated as generalized equations for current reference calculation. A simple, but general, implementation is therefore achieved, where the control objective and the power flow characteristics can be selected according to the requirements of any particular application. Thus, the same control structure can be used to achieve for instance balanced sinusoidal currents or elimination of double frequency active power oscillations during unbalanced conditions. In case of voltage sags, current references corresponding to a specified active or reactive power flow might exceed the current capability of the converter. The limits for active and reactive power transfer during unbalanced conditions have therefore been analyzed, and generalized strategies for current reference calculation when operating under current limitations have been derived. The specified objectives for active and reactive power flow characteristics can therefore be maintained during unbalanced grid conditions, while the average active and reactive power flow is limited to keep the current references within safe values. All concepts and techniques proposed in this Thesis have been verified by simulations and laboratory experiments. The SOGI-based method for Virtual Flux estimation and the strategies for active and reactive power control with current limitation can also be easily adapted for a wide range of applications and can be combined with various types of inner loop control structures. Therefore, the proposed approach can potentially be used as a general basis for Virtual Flux-based voltage-sensor-less operation of VSCs under unbalanced grid voltage conditions.

The performance of low latency Network on Chip (NoC) architectures, which incorporate fast bypass paths to reduce communication latency, is limited by crosstalk induced skewing of signal transitions on link wires. As a result of crosstalk interactions between wires, signal transitions belonging to the same flit or bit vector arrive at the destination at different times and are likely to violate setup and hold time constraints for the design. This thesis proposes a two-step technique: TransSync- RecSync, to dynamically eliminate packet errors resulting from inter-bit-line transition skew. The proposed approach adds minimally to router complexity and involves no wire overhead. The actual throughput of NoC designs with asynchronous bypass designs is evaluated and the benefits of augmenting such schemes with the proposed design are studied. The TransSync, TransSync-2-lines and RecSync schemes described here are found to improve the average communication latency by 26%, 20% and 38% respectively in a 7X7 mesh NoC with asynchronous bypass channel. This work also evaluates the bit-error ratio (BER) performance of several existing crosstalk avoidance and error correcting schemes and compares them to that of the proposed schemes. Both TransSync and RecSync scheme are dynamic in nature and can be switched on and off on-the-fly. The proposed schemes can therefore be employed to impart unequal error protection (UEP) against intra-flit skewing on NoC links. In the UEP, a larger fraction of the energy budget is spent in providing protection to those parts of the data being transmitted on the link which have a higher priority, while expending smaller effort in protecting relatively less important parts of the data. This allows us to achieve the prescribed level of performance with lower levels of power. The benefits of the presented technique are illustrated using an H.264 video decoder system-on-chip (SoC) employing NoC architecture. We show that for Akyio test streams transmitted over 3mm long link wires, the power consumption can be reduced by as much as 20% at the cost of an acceptable degradation in average peak signal to noise ratio (PSNR) with UEP.

Today's advanced digital devices are enormously complex and incorporate many functions. In order to capture the system functionality and to be able to analyze the needs for a final implementation more efficiently, the entry point of the system development process is pushed to a higher level of abstraction. System level design methodologies describe the initial system model without considering lower level implementation details and the objective of the design development process is to introduce lower level details through design refinement. In practice this kind of refinement process may entail non-semantic-preserving changes in the system description, and introduce new behaviors in the system functionality. In spite of new behaviors, a model formed by the refinement may still satisfy the design constraints and to realize the expected system. Due to the size of the involved models and the huge abstraction gap, the direct verification of a detailed implementation model against the abstract system model is quite impossible. However, the verification task can be considerably simplified, if each refinement step and its local implications are verified separately. One main idea of the Formal System Design (ForSyDe) methodology is to break the design process into smaller refinement steps that can be individually understood, analyzed and verified. The topic of this thesis is the verification of refinement steps in ForSyDe and similar methodologies. It proposes verification attributes attached to each non-semantic-preserving transformation. The attributes include critical properties that have to be preserved by transformations. Verification properties are defined as temporal logic expressions and the actual verification is done with the SMV model checker. The mapping rules of ForSyDe models to the SMV language are provided. In addition to properties, the verification attributes include abstraction techniques to reduce the size of the models and to make verification tractable. For computation refinements, the author defines the polynomial abstraction technique, that addresses verification of DSP applications at a high abstraction level. Due to the size of models, predefined properties target only the local correctness of refined design blocks and the global influence has to be examined separately. In order to compensate the influence of temporal refinements, the thesis provides two novel synchronization techniques. The proposed verification and synchronization techniques have been applied to relevant applications in the computation area and to communication protocols. / QC 20100816

Efficient algorithms for time synchronization, including compensation for clock drift, are essential in order to obtain reliable fusion of data samples from multiple wireless sensor nodes. This paper evaluates the performance of algorithms based on three different approaches; one that synchronizes the local clocks on the sensor nodes, and a second that uses a single clock on the receiving node (e.g. a mobile phone), and a third that uses broadcast messages. The performances of the synchronization algorithms are evaluated in wireless personal area networks, especially Bluetooth piconets and ZigBee/IEEE 802.15.4 networks. A new approach for compensation of clock drift and a realtime implementation of single node synchronization from the mobile phone are presented and tested. Finally, applications of data fusion and time synchronization are shown in two different use cases; a kayaking sports case, and monitoring of heart and respiration of prematurely born infants. / <p>QC 20130605</p>