International Telemetering Conference Proceedings / October 29-November 02, 1990 / Riviera Hotel and Convention Center, Las Vegas, Nevada / As the code length is increasing, the search of optimum group sync codes will be more and more difficult, even impossible. This paper gives the searching method of quasi-optimum group sync codes on the small subset of PN sequences -- CVT-TAIL SEARCHING METHOD and PREFIX-SUFFIX SEARCHING METHOD. We have searched out quasi-optimum group sync codes for their lengths N=32-63 by this method and compared them with corresponding optimum group sync codes for their lengths N=32-54. They are very approximative. The total searching time is only several seconds. This method may solves the problems among error sync probability, code length and searching time. So, it is a good and practicable searching method for long code.

International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Shortened cyclic codes are not cyclic, but many cyclic shifts of various code words are still part of the shortened code set. This paper addresses the probability of false synchronization obtained through polynomial division of a serial shortened cyclic code stream in a “sliding” window correlator.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / The UTTR (Utah Test & Training Range) offers the largest over land test and training airspace in the continental United States. It provides excellent telemetry data processing capability through a number of TM (telemetry) sites. Selecting the best source of telemetry data for optimum coverage from these many sites can be very involved and challenging for ground station personnel. Computer-based best source selection automates this process, thereby increasing accuracy and efficiency. This paper discusses the capabilities of the BTSS (Best Telemetry Source Selector), its background, design and development, applications, and future at the UTTR.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / The four-quadrant frequency discriminator (FQFD) plays an important role in GPS receivers for carrier synchronization. This paper presents a detailed study of the operating principle of the FQFD, and the acquisition performance degradation due to the gain fluctuation of the FQFD is discussed. A modified FQFD called the enveloped-four-quadrant frequency discriminator (Enveloped-FQFD) is proposed, which introduces an envelope calculator on the basis of the FQFD. Performance comparison of the FQFD and the Enveloped-FQFD is given through theoretical analysis and computer simulation. Simulation results show that by employing the Enveloped-FQFD, a quicker pull-in process and a wider threshold than the FQFD can be achieved, while the additional hardware costs are trivial.

The circadian system in mammals is arranged as a hierarchical network of oscillators, with the master pacemaker of circadian rhythms located in the suprachiasmatic nuclei (SCN) of the hypothalamus and peripheral oscillators in most other organ and tissue systems of the body. The molecular machinery responsible for generating circadian rhythms is composed of interlocked transcriptional-translational feedback loops with the gene Brain Muscle Arnt-like 1 (Bmal1) functioning as a core positive regulator. Using the mouse, Mus musculus as a model system, we studied the post-transcriptional mechanisms regulating Bmal1 expression in the SCN pacemaker and in peripheral oscillators. Target prediction algorithms were used to identify microRNAs (miRNAs) predicted to target Bmal1. We profiled the temporal expression of miR-142-3p in the mouse SCN in vivo and in an immortalized SCN cell line and observed robust circadian rhythms in its expression in the SCN. Following luciferase-reporter and site-directed mutagenesis analyses, we identified miR-142-3p as a bona-fide post-transcriptional repressor of Bmal1. The temporal expression of potential Bmal1-targeting miRNAs was also examined in the circulation in mouse serum. In mice housed in a light-dark cycle, diurnal oscillations were observed in serum levels of miR-152 and miR-494, but not miR-142-3p expression. Luciferase reporter studies indicated that miR-494, both independently and synergistically with miR-142-3p, repressed the Bmal1 3′ UTR. Overexpression of these miRNAs disrupted ensemble circadian rhythms of PER2::LUCIFERASE activity in cultured fibroblasts. Overexpression of the miRNAs also increased their extracellular levels and their intracellular accumulation in recipient cultures exposed to conditioned medium. Furthermore, inhibition of exocytosis and endocytosis affected ensemble circadian rhythms in cultured fibroblasts. The results thus implicate miR-142-3p and miR-494 in the regulation of Bmal1 expression in the SCN and peripheral oscillators and suggest that miRNAs may function as both, intracellular and extracellular (cis- and trans- acting) signals, modulating the core clock mechanism in the SCN and in fine-tuning the synchronization of circadian rhythmicity between cell-autonomous oscillators in the periphery.

Ultra high frequency (UHF) radio frequency identification (RFID) systems suffer from issues that limit their widespread deployment and limit the number of applications where they can be used. These limitations are: lack of a well defined read zone, interference, and environment sensitivity. To overcome these limitations a novel receiver device is introduced into the system. The use of such device or devices mitigates the issues by enabling more "anchor points" in the system. Two such devices exist in industry and academia: the Astraion Sensatag and the Gen2 Listener. The drawbacks of the Sensatag is that it offers poor performance in capturing tag signals. The Gen2 Listener is based on the expensive software defined radio hardware. The purpose of the thesis was to develop a receiver that will enable several new RFID applications that are not available with current RFID systems. The receiver, named ARR (Augmented RFID Receiver), receives tag and reader signals, which are decoded by an FPGA and the results are reported through Ethernet. This device is central to the augmented RFID system. To show the suitability of such an approach, the performance of the implementation was compared to the other two outlined solutions. A comparison of the read rate and range of the implementations were the defining factors. The analysis showed that the ARR is capable of receiving tag signals with a read rate of 50% for passive and 66% for semi-passive tags at a one meter distance and is capable of receiving tag signals at a maximum of 3.25 meters for passive and 5.5 meters for semi- passive tags, with the reader being within 8 meters of the ARR. Two applications were implemented to showcase the ARR: an RFID portal and protocol analyzer.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / To support initiatives for cheaper, faster, better ground telemetry systems, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center is developing a new Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) targeted to dramatically lower the cost of telemetry frame synchronization. This single VLSI device, known as the Parallel Integrated Frame Synchronizer (PIFS) chip, integrates most of the functionality contained in high density 9U VME card frame synchronizer subsystems currently in use. In 1987, a first generation 20 Mbps VMEBus frame synchronizer based on 2.0 micron CMOS VLSI technology was developed by Data Systems Technology Division. In 1990, this subsystem architecture was recast using 0.8 micron ECL & GaAs VLSI to achieve 300 Mbps performance. The PIFS chip, based on 0.7 micron CMOS technology, will provide a superset of the current VMEBus subsystem functions at rates up to 500 Mbps at approximately one-tenth current replication costs. Functions performed by this third generation device include true and inverted 64 bit marker correlation with programmable error tolerances, programmable frame length and marker patterns, programmable search-check-lock-flywheel acquisition strategy, slip detection, and CRC error detection. Acquired frames can optionally be annotated with quality trailer and time stamp. A comprehensive set of cumulative accounting registers are provided on-chip for data quality monitoring. Prototypes of the PIFS chip are expected in October 1995. This paper will describe the architecture and implementation of this new low-cost high functionality device.

Il y a présentement de la demande dans plusieurs milieux cherchant à utiliser des robots afin d'accomplir des tâches complexes, par exemple l'industrie de la construction désire des travailleurs pouvant travailler 24/7 ou encore effectuer des operation de sauvetage dans des zones compromises et dangereuses pour l'humain. Dans ces situations, il devient très important de pouvoir transporter des charges dans des environnements encombrés. Bien que ces dernières années il y a eu quelques études destinées à la navigation de robots dans ce type d'environnements, seulement quelques-unes d'entre elles ont abordé le problème de robots pouvant naviguer en déplaçant un objet volumineux ou lourd. Ceci est particulièrement utile pour transporter des charges ayant de poids et de formes variables, sans avoir à modifier physiquement le robot. Un robot humanoïde est une des plateformes disponibles afin d'effectuer efficacement ce type de transport. Celui-ci a, entre autres, l'avantage d'avoir des bras et ils peuvent donc les utiliser afin de manipuler précisément les objets à transporter. Dans ce mémoire de maîtrise, deux différentes techniques sont présentées. Dans la première partie, nous présentons un système inspiré par l'utilisation répandue de chariots de fortune par les humains. Celle-ci répond au problème d'un robot humanoïde naviguant dans un environnement encombré tout en déplaçant une charge lourde qui se trouve sur un chariot de fortune. Nous présentons un système de navigation complet, de la construction incrémentale d'une carte de l'environnement et du calcul des trajectoires sans collision à la commande pour exécuter ces trajectoires. Les principaux points présentés sont : 1) le contrôle de tout le corps permettant au robot humanoïde d'utiliser ses mains et ses bras pour contrôler les mouvements du système à chariot (par exemple, lors de virages serrés) ; 2) une approche sans capteur pour automatiquement sélectionner le jeu approprié de primitives en fonction du poids de la charge ; 3) un algorithme de planification de mouvement qui génère une trajectoire sans collisions en utilisant le jeu de primitive approprié et la carte construite de l'environnement ; 4) une technique de filtrage efficace permettant d'ignorer le chariot et le poids situés dans le champ de vue du robot tout en améliorant les performances générales des algorithmes de SLAM (Simultaneous Localization and Mapping) défini ; et 5) un processus continu et cohérent d'odométrie formés en fusionnant les informations visuelles et celles de l'odométrie du robot. Finalement, nous présentons des expériences menées sur un robot Nao, équipé d'un capteur RGB-D monté sur sa tête, poussant un chariot avec différentes masses. Nos expériences montrent que la charge utile peut être significativement augmentée sans changer physiquement le robot, et donc qu'il est possible d'augmenter la capacité du robot humanoïde dans des situations réelles. Dans la seconde partie, nous abordons le problème de faire naviguer deux robots humanoïdes dans un environnement encombré tout en transportant un très grand objet qui ne peut tout simplement pas être déplacé par un seul robot. Dans cette partie, plusieurs algorithmes et concepts présentés dans la partie précédente sont réutilisés et modifiés afin de convenir à un système comportant deux robot humanoides. Entre autres, nous avons un algorithme de planification de mouvement multi-robots utilisant un espace d'états à faible dimension afin de trouver une trajectoire sans obstacle en utilisant la carte construite de l'environnement, ainsi qu'un contrôle en temps réel efficace de tout le corps pour contrôler les mouvements du système robot-objet-robot en boucle fermée. Aussi, plusieurs systèmes ont été ajoutés, tels que la synchronisation utilisant le décalage relatif des robots, la projection des robots sur la base de leur position des mains ainsi que l'erreur de rétroaction visuelle calculée à partir de la caméra frontale du robot. Encore une fois, nous présentons des expériences faites sur des robots Nao équipés de capteurs RGB-D montés sur leurs têtes, se déplaçant avec un objet tout en contournant d'obstacles. Nos expériences montrent qu'un objet de taille non négligeable peut être transporté sans changer physiquement le robot.

This document examines the theory behind the process leading to my paintings, as well as the content of the images I use. The former will invoke romanticism, infinite possibilities, and the need for having certain parameters and flexible rules. The latter will talk about sentimentality and contemporary culture. I will explain the mechanics of justifying the choice of a particular way of painting: the push and pull between the loaded content of an image versus the language of painting itself.

Read-Modify-Write (RMW) operations, or atomics, have widespread application in (a) synchronization, where they are used as building blocks of various synchronization constructs like locks, barriers, and lock-free data structures (b) supervised memory systems, where every memory operation is effectively an RMW that reads and modifies metadata associated with memory addresses and (c) profiling, where RMW instructions are used to increment shared counters to convey meaningful statistics about a program. In each of these scenarios, the RMWs pose a bottleneck to performance and scalability. We observed that the cost of RMWs is dependent on two major factors – the memory ordering enforced by the RMW, and contention amongst processors performing RMWs to the same memory address. In the case of both synchronization and supervised memory systems, the RMWs are expensive due to the memory ordering enforced due to the atomic RMW operation. Performance overhead due to contention is more prevalent in parallel programs which frequently make use of RMWs to update concurrent data structures in a non-blocking manner. Such programs also suffer from a degradation in fairness amongst concurrent processors. In this thesis, we study the cost of RMWs in the above applications, and present solutions to obtain better performance and scalability from RMW operations. Firstly, this thesis tackles the large overhead of RMW instructions when used for synchronization in the widely used x86 processor architectures, like in Intel, AMD, and Sun processors. The x86 processor architecture implements a variation of the Total-Store-Order (TSO) memory consistency model. RMW instructions in existing TSO architectures (we call them type-1 RMW) are ordered like memory fences, which makes them expensive. The strong fence-like ordering of type-1 RMWs is unnecessary for the memory ordering required by synchronization. We propose weaker RMW instructions for TSO consistency; we consider two weaker definitions: type-2 and type-3, each causing subtle ordering differences. Type-2 and type-3 RMWs avoid the fence-like ordering of type-1 RMWs, thereby reducing their overhead. Recent work has shown that the new C/C++11 memory consistency model can be realized by generating type-1 RMWs for SC-atomic-writes and/or SC-atomic-reads. We formally prove that this is equally valid for the proposed type-2 RMWs, and partially for type-3 RMWs. We also propose efficient implementations for type-2 (type-3) RMWs. Simulation results show that our implementation reduces the cost of an RMW by up to 58.9% (64.3%), which translates into an overall performance improvement of up to 9.0% (9.2%) for the programs considered. Next, we argue the case for an efficient and correct supervised memory system for the TSO memory consistency model. Supervised memory systems make use of RMW-like supervised memory instructions (SMIs) to atomically update metadata associated with every memory address used by an application program. Such a system is used to help increase reliability, security and accuracy of parallel programs by offering debugging/monitoring features. Most existing supervised memory systems assume a sequentially consistent memory. For weaker consistency models, like TSO, correctness issues (like imprecise exceptions) arise if the ordering requirement of SMIs is neglected. In this thesis, we show that it is sufficient for supervised instructions to only read and process their metadata in order to ensure correctness. We propose SuperCoP, a supervised memory system for relaxed memory models in which SMIs read and process metadata before retirement, while allowing data and metadata writes to retire into the write-buffer. Our experimental results show that SuperCoP performs better than the existing state-of-the-art correct supervision system by 16.8%. Finally, we address the issue of contention and contention-based failure of RMWs in non-blocking synchronization mechanisms. We leverage the fact that most existing lock-free programs make use of compare-and-swap (CAS) loops to access the concurrent data structure. We propose DyFCoM (Dynamic Fairness and Contention Management), a holistic scheme which addresses both throughput and fairness under increased contention. DyFCoM monitors the number of successful and failed RMWs in each thread, and uses this information to implement a dynamic backoff scheme to optimize throughput. We also use this information to throttle faster threads and give slower threads a higher chance of performing their lock-free operations, to increase fairness among threads. Our experimental results show that our contention management scheme alone performs better than the existing state-of-the-art CAS contention management scheme by an average of 7.9%. When fairness management is included, our scheme provides an average of 3.4% performance improvement over the constant backoff scheme, while showing increased fairness values in all cases (up to 43.6%).