As single-chip systems are predicted to soon contain over a billion transistors, design methodologies are evolving dramatically to account for the fast evolution of technologies and product properties. Novel methodologies feature the exploration of design alternatives early in development, the support for IPs, and early error detection — all with a decreasing time-to-market. In order to accommodate these product complexities and development needs, the modeling levels at which designers are working have quickly changed, as development at higher levels of abstraction allows for faster simulations of system models and earlier estimates of system performance while considering design trade-offs. Recent design advancements to exploit instruction-level parallelism on single-processor computer systems have become exceedingly complex, and modern applications are presenting an increasing potential to be partitioned and parallelized at the thread level. The new Single-Chip, Message-Passing (SCMP) parallel computer is a tightly coupled mesh of processing nodes that is designed to exploit thread-level parallelism as efficiently as possible. By minimizing the latency of communication among processors, memory access time, and the time for context switching, the system designer will undoubtedly observe an overall performance increase. This study presents in-depth evaluations and quantitative analyses of various design and performance aspects of SCMP through the development of abstract hardware models by following a formalized, well-defined methodology. The performance evaluations are taken through benchmark simulation while taking into account system-level communication and synchronization among nodes as well as node-level timing and interaction amongst node components. Through the exploration of alternatives and optimization of the components within the SCMP models, maximum system performance in the hardware implementation can be achieved. / Master of Science

Avec l'essor des nouvelles technologies d'intégration sur silicium submicroniques, la consommation de puissance dans les systèmes sur puce multiprocesseur (MPSoC) est devenue un facteur primordial au niveau du flot de conception. La prise en considération de ce facteur clé dés les premières phases de conception, joue un rôle primordial puisqu'elle permet d'augmenter la fiabilité des composants et de réduire le temps d'arrivée sur le marché du produit final. Dans cette thèse, nous proposons une méthodologie efficace pour l'estimation de la consommation de puissance des plateformes MPSoC. Cette méthodologie repose sur une combinaison d'une analyse fonctionnelle de la puissance (FLPA) pour l'obtention des modèles de consommation et d'une technique de simulation au niveau transactionnel (TLM) pour calculer la puissance de l'ensemble du système. Fondamentalement, FLPA est proposée pour modéliser le comportement des processeurs en terme de consommation afin d'obtenir des modèles paramétrés de haut niveau. Dans ce travail, FLPA est étendue pour mettre en place des modèles de puissance génériques pour les différentes parties du système (mémoire, logique reconfigurable, etc.). En outre, un environnement de simulation a été développé au niveau transactionnel afin d'évaluer avec précision les activités utilisées dans les modèles de consommation. La combinaison de ces deux parties conduit à une estimation de la puissance hybride qui donne un meilleur compromis entre la précision et la vitesse. La méthodologie proposée a plusieurs avantages: elle estime la consommation du système embarqué dans tous ses éléments et conduit à des estimations précises sans matériel coûteux et complexe. La méthodologie proposée est évolutive pour explorer des architectures complexes embarquées. Notre outil d'estimation de puissance au niveau du système PETS (Power Estimation Tool at System-level) est développé sur la base de la méthodologie proposée. L'efficacité de notre outil PETS en termes de précision et rapidité est validée par des architectures embarquées monoprocesseur et multiprocesseur conçues autour des plateformes OMAP (3530 et 5912) et FPGA Pro Xilinx Virtex II.

Thesis advisor: Lauri Johnson / District leadership has been found to have a measurable effect on student achievement by creating conditions within which teachers and administrators frame their daily work with children. The superintendent is uniquely poised to build the needed infrastructure of support and assure its alignment with the philosophy and mission of the district and, in turn, with the work of the school. By attending to the habits and conditions that allow a staff to work as a unit, superintendents are able to contribute to the development of a community of professional learners within and among district schools. This qualitative case study analyzed district leadership practices that support ongoing teacher growth in a Massachusetts school district by examining the work of the superintendent and the impact of his leadership on the ongoing development of a community of professional learners at the district and school level. Data included interviews with teachers and administrators, artifact analyses, and observations of district meetings. Findings reveal the superintendent's use of a PLC process to model and provide support to school-level leaders by encouraging broad-based participation in the skillful work of leadership; establishing a clear vision which resulted in program coherence; fostering a system of inquiry-based accountability that informed decision making and practice; and nurturing organizational relationships that involved high district engagement and low bureaucratization which supported school-based collaborative teacher growth. / Thesis (EdD) — Boston College, 2014. / Submitted to: Boston College. Lynch School of Education. / Discipline: Educational Leadership and Higher Education.

The present study examined the relationship between the occurrence of reported supervision and the professional practices of school psychologists. Information provided by more than 1,700 school psychologists in response to the National Association of School Psychologists: Demographic and Professional Practices Survey 1999-2000 School Year - NASP-DPPS 2000 survey were used to create the 1999-2000 national database (Curtis, et al., 2000) and served as the basis for secondary analyses in the current study. The NASPDPPS 2000 collected information regarding the demographic characteristics, employment conditions and professional practices of school psychologists the United States. Correlational and multiple regression analyses were completed to examine the relationship between professional practices and the reported receipt of supervision, background of the supervisor, and ratio of school psychologists to supervisor. Professional practices did not appear to be significantly related to vary as a function of the occurrence of reported supervision. School psychologists reporting receiving supervision completed significantly more initial psychoeducational assessment and reevaluations than school psychologists who reported not receiving supervision. Initial pyshcoeducational assessment and reevaluations are professional practices that can be categorized as special education and direct service delivery model. The subsample of school psychologists who reported the occurrence of supervision was examined for the remaining analyses. In addition, supervised school psychologists' professional practices did not vary as a function the supervisor's type of educational background (i.e., school psychology or non-school psychology), and level of educational preparation (i.e., doctoral or nondoctoral). Finally, the school psychologists-to-supervisor ratio and nature of the school psychologists' professional practices was examined. The remaining correlations were considered non-significant. It was noted that the questions included in the NASP-DPPS 2000 survey did not allow for specific information about the type, topography, or quality of supervision. This limitation precluded drawing specific conclusions regarding the research questions addressed.

<p>Multithreading is a processor technique that can effectively hide long latencies that can occur due to memory accesses, coprocessor operations and similar. While this looks promising, there is an additional hardware cost that will vary with for example the number of contexts to switch to and what technique is used for it and this might limit the possible gain of multithreading.</p><p>Network processors are, traditionally, multiprocessor systems that share a lot of common resources, such as memories and coprocessors, so the potential gain of multithreading could be high for these applications. On the other hand, the increased hardware required will be relatively high since the rest of the processor is fairly small. Instead of having a multithreaded processor, higher performance gains could be achieved by using more processors instead.</p><p>As a solution, a simulator was built where a system can effectively be modelled and where the simulation results can give hints of the optimal solution for a system in the early design phase of a network processor system. A theoretical background to multithreading, network processors and more is also provided in the thesis.</p>

<p>The DMA(direct memory access) controller is a special component in DSP processor used to offload the data transferring from CPU and improve the data access efficiency in the microprocessor.</p><p>This paper describes the design and implementation of DMA(direct memory access) device for microprocessor developed using C++ Language and SystemC libraries. The main facts covered within this report are the structure of a microprocessor with embedded DMA, and some interesting points of SystemC and TLM library that are useful for the design and implementation of the system level design.</p><p>This paper starts with an introduction of the theory of DMA , the structure of the microprocessor and the multicore microprocessor. Next it goes further into the DMA specification discussion. The next chapter is the implementation of DMA and the microsystem, later on in this chapter is an explanation of the SystemC methods I used in the system design.</p><p>At last, the simulation results of the whole system is presented and analyzed. The utility of the DMA is discussed and calculated.</p><p>With all these aspects covered in the paper, it is easy for the readers to understand the DMA theory , micro architecture as well as the fundamental knowledge of SystemC.</p>

<p>Den säkerhetspolitiska debatten har under de senaste åren tillvaratagit ett bredare perspektiv av hot och risker. Undersökningen tar sin utgångspunkt i frågan om i vilken utsträckning detta kommit till uttryck i svenska försvarspropositioner?</p><p> </p><p>Undersökningen kartlägger likheter och skillnader i tre försvarspropositioners uttryck av hot och säkerhet relaterat till det vidgade säkerhetsbegreppet under perioden 1982-2009. Vid kartläggningen undersöker jag med hjälp av Barry Buzan m.fl. analysramverk för det vidgade säkerhetsbegreppet vilka säkerhetspolitiska värden som uttrycktes vara viktiga att säkerställa. Undersökningen kartlägger även hotbilderna som uppfattades mot dessa värden och inom vilka arenor deras säkerhet bedömdes kunna säkerställas.</p><p>Analysen påvisar olikheter i de tre försvarspropositionernas säkerhetspolitiska uttryck. 1982 års försvarsproposition fokuserar på nationella säkerhetspolitiska värden som säkerställdes inom totalförsvarets ram. De följande försvarspropositionerna indikerar en förändring till förmån för regionala värden och gemensam säkerhet. Analysen påvisar även en radikal förändring av de uppfattade hotbildernas karaktär.</p> / <p>The recent security policy debate has included a broader view of threats and risks. This study is based on the question of to what extent this was reflected in the Swedish defence bills?</p><p>This study aims to identify similarities and differences regarding expressions of threat and security related to the broader concept of security in three defence bills over the period of 1982-2009. By use of the analytical framework of Mr Barry Buzan, I aim to make a survey of the expressed values of security, their perceived threats and the arenas in which their security were to be guaranteed.</p><p>The analysis indicates diversities regarding security policy expressions. The defence bill of 1982 focuses on national values, safeguarded within the framework of Total Defence. The following defence bills indicate a change in the perceived nature of the threats and in favour of regional values and common security.</p>

Since the development of SoC is very fast, how to reduce the power consumption of SoC and improve the performance of SoC has become a very important issue. The power consumption of a system depends upon the hardware and software of a system. To overcome the issue of power consumption, the hardware circuit provides multi-voltage method to reduce task power consumption. On the other hand, the software tool decides the exact voltage for each task to minimize the total power consumption and finds a pipelined schedule of the periodic tasks to enhance the total throughput. In this thesis, a Tabu search is used to solve the voltage mapping and resource mapping problems of multi-voltage systems. This goal of this Tabu search is to find the solution with minimal power consumption for the multi-voltage system under the time constraints and resource constraints at the same time in the multi-voltage system to. Under the throughput constraints we use Tabu search to find solutions including the task¡¦s execution voltage and resource mapping, and then use list pipelined scheduling to schedule task and data communication and check their correctness. This method can reduce total power consumption. Experimental results show that our proposed algorithm can decide the resources mapping and pipeline in seconds, and it can reduce the power consumption efficiently.

This thesis addresses several issues related to the design and optimization of embedded systems. In particular, in the context of time-constrained embedded systems, the thesis investigates two problems: the minimization of the energy consumption and the implementation of predictable applications on multiprocessor system-on-chip platforms. Power consumption is one of the most limiting factors in electronic systems today. Two techniques that have been shown to reduce the power consumption effectively are dynamic voltage selection and adaptive body biasing. The reduction is achieved by dynamically adjusting the voltage and performance settings according to the application needs. Energy minimization is addressed using both offline and online optimization approaches. Offline, we solve optimally the combined supply voltage and body bias selection problem for multiprocessor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. The voltage selection technique is applied not only to processors, but also to buses with repeaters and fat wires. We investigate the continuous voltage selection as well as its discrete counterpart. While the above mentioned methods minimize the active energy, we propose an approach that combines voltage selection and processor shutdown in order to optimize the total energy. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the voltage and performance settings during run-time, i.e., online. However, voltage scaling is computationally expensive, and, thus, performed at runtime, significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static voltage scaling scheme, with a constant online time complexity O(1). This allows to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the voltage settings. Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system’s communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks’ WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we propose, an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures.

Den säkerhetspolitiska debatten har under de senaste åren tillvaratagit ett bredare perspektiv av hot och risker. Undersökningen tar sin utgångspunkt i frågan om i vilken utsträckning detta kommit till uttryck i svenska försvarspropositioner?   Undersökningen kartlägger likheter och skillnader i tre försvarspropositioners uttryck av hot och säkerhet relaterat till det vidgade säkerhetsbegreppet under perioden 1982-2009. Vid kartläggningen undersöker jag med hjälp av Barry Buzan m.fl. analysramverk för det vidgade säkerhetsbegreppet vilka säkerhetspolitiska värden som uttrycktes vara viktiga att säkerställa. Undersökningen kartlägger även hotbilderna som uppfattades mot dessa värden och inom vilka arenor deras säkerhet bedömdes kunna säkerställas. Analysen påvisar olikheter i de tre försvarspropositionernas säkerhetspolitiska uttryck. 1982 års försvarsproposition fokuserar på nationella säkerhetspolitiska värden som säkerställdes inom totalförsvarets ram. De följande försvarspropositionerna indikerar en förändring till förmån för regionala värden och gemensam säkerhet. Analysen påvisar även en radikal förändring av de uppfattade hotbildernas karaktär. / The recent security policy debate has included a broader view of threats and risks. This study is based on the question of to what extent this was reflected in the Swedish defence bills? This study aims to identify similarities and differences regarding expressions of threat and security related to the broader concept of security in three defence bills over the period of 1982-2009. By use of the analytical framework of Mr Barry Buzan, I aim to make a survey of the expressed values of security, their perceived threats and the arenas in which their security were to be guaranteed. The analysis indicates diversities regarding security policy expressions. The defence bill of 1982 focuses on national values, safeguarded within the framework of Total Defence. The following defence bills indicate a change in the perceived nature of the threats and in favour of regional values and common security.