The unabated continuation of the Moore's law has allowed the doubling of the number of transistors per unit area of a silicon die every 2 years or so. At the same time, an increasing demand on consumer electronics and computing equipments to run sophisticated applications has led to an unprecedented complexity of hardware designs. These factors have necessitated the abstraction level of design-entry of hardware systems to be raised beyond the Register-Transfer-Level (RTL) to Electronic System Level (ESL). However, power envelope on the designs due to packaging and other thermal limitations, and the energy envelope due to battery life-time considerations have also created a need for power/energy efficient design. The confluence of these two technological issues has created an urgent need for solving two problems: (i) How do we enable a power-aware design flow with a design entry point at the Electronic System Level? (ii) How do we enable power aware High Level Synthesis to automatically synthesize RTL implementation from ESL? This dissertation distinguishes itself by addressing the following two issues: (i) Since power/energy consumption of electronic systems largely depends on implementation details, and high-level models abstract away from such details, power/energy estimation at such levels has not been addressed thoroughly. (ii) A lot of work has been done in applying various techniques on control-data-flow graphs (CDFG) to find power/area/latency pareto points during behavioral synthesis. However, high level C-based functional models of various compute-intensive components, which could be easily synthesized as co-processors, have many opportunities to reduce power. Some of these savings opportunities are traditional such as clock-gating, operand-isolation etc. The exploration of alternate granularities of these techniques with target applications in mind, opens the door for traditional power reduction opportunities at the high-level. This work therefore concentrates on the aforementioned two areas of inadequacy of hardware design methodologies. Our proposed solutions include utilizing ESL simulation traces and mapping those to lower abstraction levels for power estimation, derivation of statistical power models using regression based learning for power estimation at early design stages, etc. On the HLS front, techniques that insert the power saving features during the synthesis process using exploration of granularity and scope of clock-gating, sequential clock-gating are proposed. Finally, this work shows how to marry two domains, that is estimation and reduction. In this regard, a power model is proposed, which helps in predicting power savings obtained using clock-gating and further guiding HLS to selectively insert clock-gating. / Ph. D.

This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution.

Este trabalho propõe uma nova abordagem para o desenvolvimento de sistemas embarcados, através da combinação da abstração e propriedades de verificação de modelos da linguagem declarativa Alloy com a ampla aceitação de Java na indústria. A abordagem surge no contexto de que a automação de software no domínio embarcado tornou-se extremamente necessária, uma vez que atualmente a maior parte do tempo de desenvolvimento é gasta no projeto de software de produtos tão restritos em termos de recursos. As ferramentas de automação de software embarcado devem atender a demanda por produtividade e manutenibilidade, mas respeitar restrições naturais deste tipo de sistema, tais como espaço de memória, potência e desempenho. As ferramentas de automação de projeto lidam com produtividade e manutenibilidade ao permitir especificações de alto nível, tarefa difícil de atender no domínio embarcado devido ao comportamento misto de muitas aplicações embarcadas. Abordagens que promovem meios para verificação formal também são atrativas, embora geralmente sejam difíceis de usar, e por este motivo não são de grande auxílio na tarefa de reduzir o tempo de chegada ao mercado do produto. Através do uso de Alloy, baseada em lógica de primeira-ordem, é possível obter especificações em altonível e verificação formal de modelos com uma única linguagem. Este trabalho apresenta a poderosa abstração proporcionada pela linguagem Alloy em aplicações embarcadas, assim como regras para obter automaticamente código Java a partir de modelos Alloy. A geração de código Java a partir de modelos Alloy, combinada a uma ferramenta de estimativa, provê exploração de espaço de projeto, atendendo assim as fortes restrições do projeto de software embarcado, o que normalmente não é contemplado pela engenharia de software tradicional. / This work proposes a new approach for embedded software development, by combining the abstraction and model verification properties of the Alloy declarative language with the broad acceptance in industry of Java. The approach comes into play since software automation in the embedded domain has become a major need, as currently most of the development time is spent designing software for such hardconstrained resources products. Design automation tools for embedded systems must meet the demand for productivity and maintainability, but constraints such as memory, power and performance must still be considered. Design automation tools deal with productivity and maintainability by allowing high-level specifications, which is hard to accomplish on the embedded domain due to the mixed behavior nature of many embedded applications. Approaches that provide means for formal verification are also attractive, but their usage is usually not straightforward, and for this reason they are not that helpful in dealing with time-tomarket constraints. By using Alloy, based in first-order logic, it is possible to obtain high-level specifications and formal model verification with a single language. This work shows the powerful abstraction provided by the Alloy language for embedded applications, as well as rules for obtaining automatically Java code from Alloy models. The Java source code generation from Alloy models, combined with an estimation tool, provides design space exploration to match tight embedded software design constraints, what is usually not taken into account by standard software engineering techniques.

A system packaging level approach on liquid crystal polymer (LCP) was proposed for low cost, lightweight, and compact wireless communication systems. Via technology was explored for V-band W-band transitions and an active cooling system that are essential for compact multilayer integration. RF MEMS switches were fabricated and integrated at the component level to enable multi-functional devices with optimal performance. A pattern reconfigurable antenna for MIMO applications and 3D phase shifters for phased array antennas that use RF MEMS switches were presented. In addition, a lightweight expandable array was designed and measured with up to 256 elements on multilayer LCP integrated at the system level. Furthermore, a 60 GHz multilayer transceiver front end device with simultaneous transmit and receive was designed and measured for low cost 60 GHz applications. The wide variety of multilayer LCP applications integrated at the system level shows a promising future for the next generation low cost lightweight wireless communication systems.

The United States Navy is committed to developing technology for an All-Electric Ship (AES) that promises to improve the affordability and capability of its next-generation warships. With the addition of power-intensive 21st century electrical systems, future thermal loads are projected to exceed current heat removal capacity. Furthermore, rising fuel costs necessitate a careful approach to total-ship energy management. Accordingly, the aim of this research is to develop computer tools for early-stage design of shipboard energy distribution systems. A system-level model is developed that enables ship designers to assess the effects of thermal and electrical system configurations on fuel efficiency and survivability. System-level optimization and design exploration, based on these energy system models, is challenging because the models are sometimes computationally expensive and characterized by discrete design variables and discontinuous responses. To address this challenge, a classifier-guided sampling (CGS) method is developed that uses a Bayesian classifier to pursue solutions with desirable performance characteristics. The CGS method is tested on a set of example problems and applied to the AES energy system model. Results show that the CGS method significantly improves the rate of convergence towards known global optima, on average, when compared to genetic algorithms. / text

The current trend in embedded systems design is to move the initial design and exploration phase to a higher level of abstraction, in order to tackle the rapidly increasing complexity of embedded systems. One approach of abstracting software development from the low level platform details is host- compiled simulation. Characteristics of the target platform are represented in a host-compiled simulation model by annotating the high level source code. Compiler optimizations make accurate annotation of the code a challenging task. In this thesis, we describe an approach to enable correct back-annotation of C code at the basic block level, while taking compiler optimizations into account. / text

Condition-Based Maintenance (CBM) and Prognostics and Health Management (PHM) technologies aim at improving the availability, reliability, maintainability, and safety of systems through the development of fault diagnostic and failure prognostic algorithms. In complex engineering systems, such as aircraft, power plants, etc., the prognostic activities have been limited to the component-level, primarily due to the complexity of large-scale engineering systems. However, the output of these prognostic algorithms can be practically useful for the system managers, operators, or maintenance personnel, only if it helps them in making decisions, which are based on system-level parameters. Therefore, there is an emerging need to build health assessment methodologies at the system-level. This research employs techniques from the field of design-of-experiments to build response surface metamodels at the system-level that are built on the foundations provided by component-level damage models.

The broad aim of this research is to contribute knowledge that enables improvements in how designers model decision alternatives at the systems level—i.e., how they model different system configurations and concepts. There are three principal complications: (1) design concepts and systems configurations are partially-defined solutions to a problem that correspond to a large set of possible design implementations, (2) each concept or configuration may operate on different physical principles, and (3) decisions typically involve tradeoffs between multiple competing objectives that can include "non-engineering" considerations such as production costs and profits. This research is an investigation of a data-driven approach to modeling partially-defined system alternatives that addresses these issues. The approach is based on compositional strategy in which designers model a system alternative using abstract models of its components. The component models are representations of the rational tradeoffs available to designers when implementing the components. Using these models, designers can predict key properties of the final implementation of each system alternative. A new construct, called a parameterized efficient set, is introduced as the decision-theoretic basis for generating the component-level tradeoff models. Appropriate efficiency criteria are defined for the cases of deterministic and uncertain data. It is shown that the model composition procedure is mathematically sound under reasonable assumptions for the case of deterministic data. This research also introduces an approach for describing the valid domain of a data-driven model based on the use of support-vector machines. Engineering examples include performing requirements allocation for a hydraulic log splitter and architecture selection for a hybrid vehicle.

Molecular recognition plays an essential role in the self-assembly and self-organisation of biological and chemical systems alike—allowing individual components to form complex interconnected networks. Within these systems, the nature of the recognition and reactive processes determines their functional and structural properties, and even small changes in their identity or orientation can exert a dramatic effect on the observed properties. The rapidly developing field of systems chemistry aims to move away from the established paradigm in which molecules are studied in isolation, towards the study of networks of molecules that interact and react with each other. Taking inspiration from complex natural systems, where recognition processes never operate in isolation, systems chemistry aims to study chemical networks with the view to examining the system-level properties that arise from the interactions and reactions between the components within these systems. The work presented in this thesis aims to advance the nascent field of systems chemistry by bringing together small organic molecules that can react and interact together to form interconnected networks, exhibiting complex behaviour, such as self-replication, as a result. Three simple building blocks are used to construct a network of two structurally similar replicators and their kinetic behaviour is probed through a comprehensive kinetic analysis. The selectivity for one of the recognition-mediated reactive processes over another is examined within the network in isolation as well as in a scenario where the network is embedded within a pool of exchanging components. The interconnected, two-replicator network is examined under far-from-equilibrium reaction-diffusion conditions, showing that chemical replicating networks can exhibit signs of selective replication—a complex phenomenon normally associated with biological systems. Finally, a design of a well-characterised replicator is exploited for the construction of a network integrating self-replication with a another recognition-directed process, leading to the formation of a mechanically-interlocked architecture—a [2]rotaxane.

Este trabalho propõe uma nova abordagem para o desenvolvimento de sistemas embarcados, através da combinação da abstração e propriedades de verificação de modelos da linguagem declarativa Alloy com a ampla aceitação de Java na indústria. A abordagem surge no contexto de que a automação de software no domínio embarcado tornou-se extremamente necessária, uma vez que atualmente a maior parte do tempo de desenvolvimento é gasta no projeto de software de produtos tão restritos em termos de recursos. As ferramentas de automação de software embarcado devem atender a demanda por produtividade e manutenibilidade, mas respeitar restrições naturais deste tipo de sistema, tais como espaço de memória, potência e desempenho. As ferramentas de automação de projeto lidam com produtividade e manutenibilidade ao permitir especificações de alto nível, tarefa difícil de atender no domínio embarcado devido ao comportamento misto de muitas aplicações embarcadas. Abordagens que promovem meios para verificação formal também são atrativas, embora geralmente sejam difíceis de usar, e por este motivo não são de grande auxílio na tarefa de reduzir o tempo de chegada ao mercado do produto. Através do uso de Alloy, baseada em lógica de primeira-ordem, é possível obter especificações em altonível e verificação formal de modelos com uma única linguagem. Este trabalho apresenta a poderosa abstração proporcionada pela linguagem Alloy em aplicações embarcadas, assim como regras para obter automaticamente código Java a partir de modelos Alloy. A geração de código Java a partir de modelos Alloy, combinada a uma ferramenta de estimativa, provê exploração de espaço de projeto, atendendo assim as fortes restrições do projeto de software embarcado, o que normalmente não é contemplado pela engenharia de software tradicional. / This work proposes a new approach for embedded software development, by combining the abstraction and model verification properties of the Alloy declarative language with the broad acceptance in industry of Java. The approach comes into play since software automation in the embedded domain has become a major need, as currently most of the development time is spent designing software for such hardconstrained resources products. Design automation tools for embedded systems must meet the demand for productivity and maintainability, but constraints such as memory, power and performance must still be considered. Design automation tools deal with productivity and maintainability by allowing high-level specifications, which is hard to accomplish on the embedded domain due to the mixed behavior nature of many embedded applications. Approaches that provide means for formal verification are also attractive, but their usage is usually not straightforward, and for this reason they are not that helpful in dealing with time-tomarket constraints. By using Alloy, based in first-order logic, it is possible to obtain high-level specifications and formal model verification with a single language. This work shows the powerful abstraction provided by the Alloy language for embedded applications, as well as rules for obtaining automatically Java code from Alloy models. The Java source code generation from Alloy models, combined with an estimation tool, provides design space exploration to match tight embedded software design constraints, what is usually not taken into account by standard software engineering techniques.