The next generation wireless networks i.e. 5G aim to provide multi-Gbps data traffic, in order to satisfy the increasing demand for high-definition video, among other high data rate services, as well as the exponential growth in mobile subscribers. To achieve this dramatic increase in data rates, current research is focused on improving the capacity of current 4G network standards, based on Long Term Evolution (LTE), before radical changes are exploited which could include acquiring additional/new spectrum. The LTE network has a reuse factor of one; hence neighbouring cells/sectors use the same spectrum, therefore making the cell edge users vulnerable to inter-cell interference. In addition, wireless transmission is commonly hindered by fading and pathloss. In this direction, this thesis focuses on improving the performance of cell edge users in LTE and LTE-Advanced (LTE-A) networks by initially implementing a new Coordinated Multi-Point (CoMP) algorithm to mitigate cell edge user interference. Subsequently Device-to-Device (D2D) communication is investigated as the enabling technology for maximising Resource Block (RB) utilisation in current 4G and emerging 5G networks. It is demonstrated that the application, as an extension to the above, of novel power control algorithms, to reduce the required D2D TX power, and multihop transmission for relaying D2D traffic, can further enhance network performance. To be able to develop the aforementioned technologies and evaluate the performance of new algorithms in emerging network scenarios, a beyond-the-state-of-the-art LTE system-level simulator (SLS) was implemented. The new simulator includes Multiple-Input Multiple-Output (MIMO) antenna functionalities, comprehensive channel models (such as Wireless World initiative New Radio II i.e. WINNER II) and adaptive modulation and coding schemes to accurately emulate the LTE and LTE-A network standards. Additionally, a novel interference modelling scheme using the 'wrap around' technique was proposed and implemented that maintained the topology of flat surfaced maps, allowing for use with cell planning tools while obtaining accurate and timely results in the SLS compared to the few existing platforms. For the proposed CoMP algorithm, the adaptive beamforming technique was employed to reduce interference on the cell edge UEs by applying Coordinated Scheduling (CoSH) between cooperating cells. Simulation results show up to 2-fold improvement in terms of throughput, and also shows SINR gain for the cell edge UEs in the cooperating cells. Furthermore, D2D communication underlaying the LTE network (and future generation of wireless networks) was investigated. The technology exploits the proximity of users in a network to achieve higher data rates with maximum RB utilisation (as the technology reuses the cellular RB simultaneously), while taking some load off the Evolved Node B (eNB) i.e. by direct communication between User Equipment (UE). Simulation results show that the proximity and transmission power of D2D transmission yields high performance gains for a D2D receiver, which was demonstrated to be better than that of cellular UEs with better channel conditions or in close proximity to the eNB in the network. The impact of interference from the simultaneous transmission however impedes the achievable data rates of cellular UEs in the network, especially at the cell edge. Thus, a power control algorithm was proposed to mitigate the impact of interference in the hybrid network (network consisting of both cellular and D2D UEs). It was implemented by setting a minimum SINR threshold so that the cellular UEs achieve a minimum performance, and equally a maximum SINR threshold to establish fairness for the D2D transmission as well. Simulation results show an increase in the cell edge throughput and notable improvement in the overall SINR distribution of UEs in the hybrid network. Additionally, multihop transmission for D2D UEs was investigated in the hybrid network: traditionally, the scheme is implemented to relay cellular traffic in a homogenous network. Contrary to most current studies where D2D UEs are employed to relay cellular traffic, the use of idle nodes to relay D2D traffic was implemented uniquely in this thesis. Simulation results show improvement in D2D receiver throughput with multihop transmission, which was significantly better than that of the same UEs performance with equivalent distance between the D2D pair when using single hop transmission.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2017-11-13T21:02:54Z No. of bitstreams: 1 Felipe_Gohring_de_Magalh?es_TES.pdf: 7728697 bytes, checksum: f2b34275e49f32253d8c38848a3d9258 (MD5) / Approved for entry into archive by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-11-21T12:14:27Z (GMT) No. of bitstreams: 1 Felipe_Gohring_de_Magalh?es_TES.pdf: 7728697 bytes, checksum: f2b34275e49f32253d8c38848a3d9258 (MD5) / Made available in DSpace on 2017-11-21T12:26:58Z (GMT). No. of bitstreams: 1 Felipe_Gohring_de_Magalh?es_TES.pdf: 7728697 bytes, checksum: f2b34275e49f32253d8c38848a3d9258 (MD5) Previous issue date: 2017-05-25 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior - CAPES / As tend?ncias de design para os sistemas multiprocessadores da pr?xima gera??o apontam para a integra??o de um grande n?mero de n?cleos de processamento, exigindo interconex?es de alto desempenho. Uma solu??o a ser aplicada para melhorar a infraestrutura de comunica??o em tais sistemas ? o uso de redes on-chip, pois estas apresentam uma melhoria consider?vel na largura de banda e escalabilidade. Ainda assim, o n?mero de n?cleos integrados continua a aumentar ao mesmo tempo em que o sistema cresce, dessa maneira as interconex?es met?licas em redes on-chip podem tornar-se um gargalo no desempenho. Como resultado, uma nova estrat?gia deve ser adotada para que essas quest?es sejam solucionadas. As Redes ?pticas Integradas (do ingl?s Optical Integrated Networks - OINs) s?o atualmente consideradas como um dos paradigmas mais promissores neste contexto de design: elas apresentam maior largura de banda, menor consumo de energia e baixa lat?ncia para transmitir informa??es. Al?m disso, trabalho recentes demonstram a viabilidade de OINs com suas tecnologias de fabrica??o dispon?veis e compat?veis com CMOS. No entanto, os designers de OINs enfrentam v?rios desafios: ? Atualmente, os controladores representam o principal gargalo na comunica??o e s?o um dos fatores que limitam o uso de OINs. Portanto, novas solu??es de controle de baixa lat?ncia s?o necess?rias. ? Designers n?o possuem ferramentas para modelar e validar OINs. A maioria das pesquisas atualmente est? focada em projetar dispositivos e melhorar os componentes b?sicos, deixando o sistema sem melhorias. Neste contexto, para facilitar a implanta??o de sistemas baseados em OIN, este projeto de doutorado concentra-se em tr?s contribui??es principais: (1) o desenvolvimento da plataforma de simula??o a n?vel de sistema; (2) a defini??o e o desenvolvimento de uma abordagem de controle eficiente para sistemas baseados em OIN e; (3) a avalia??o, a n?vel do sistema, da abordagem de controle proposta usando a modelagem definida. / Design trends for next-generation Multi-Processor Systems point to the integration of a large number of processing cores, requiring high-performance interconnects. One solution being applied to improve the communication infrastructure in such systems is the usage of Networkson- Chip as they present considerable improvement in the bandwidth and scaleability. Still as the number of integrated cores continues to increase and the system scales, the metallic interconnects in Networks-on-Chip can become a performance bottleneck. As a result, a new strategy must be adopted in order for those issues to be remedied. Optical Integrated Networks (OINs) are currently considered to be one of the most promising paradigm in this design context: they present higher bandwidth, lower power consumption and lower latency to broadcast information. Also, the latest work demonstrates the feasibility of OINs with their fabrication technologies being available and CMOS compatible. However, OINs? designers face several challenges: ? Currently, controllers represent the main communication bottleneck and are one of the factors limiting the usage of OINs. Therefore, new controlling solutions with low latency are required. ? Designers lack tools to model and validate OINs. Most research nowadays is focused on designing devices and improving basic components performance, leaving system unattended. In this context, in order to ease the deployment of OIN-based systems, this PhD project focuses on three main contributions: (1) the development of accurate system-level modelling study to realize a system-level simulation platform; (2) the definition and development of an efficient control approach for OIN-based systems, and; (3) the system-level evaluation of the proposed control approach using the defined modelling.

L'augmentation de la densité des transistors dans les circuits électroniques conduit à une augmentation de la consommation d'énergie induisant des phénomènes thermiques plus complexes à maitriser. Dans le cas de systèmes embarqués en environnement où la température ambiante varie dans des proportions importantes (automobile par exemple), ces phénomènes peuvent conduire à des problèmes de fiabilité. Parmi les mécanismes de défaillance observés, on peut citer les cycles thermiques (CT) qui induisent des déformations dans les couches métalliques de la puce pouvant conduire à des fissurations. L’objectif de la thèse est de proposer pour des architectures de type multiprocesseur sur puce une technique de réduction des CT subis par les processeurs, et ce en respectant les contraintes temps réel des applications. L’exemple du circuit MPC5517 de Freescale a été considéré. Dans un premier temps un modèle thermique de ce circuit a été élaboré à partir de mesures par une caméra thermique sur ce circuit décapsulé. Un environnement de simulation a été mis en oeuvre pour permettre d’effectuer simultanément des analyses thermiques et d’ordonnancement de tâches et mettre en évidence l’influence de la température sur la puissance dissipée. Une heuristique globale pour réduire à la fois les CT et la température maximale des processeurs a été étudiée. Elle tient compte des variations de la température ambiante et se base sur les techniques DVFS et DPM. Les résultats de simulation avec les algorithmes d’ordonnancement globaux RM, EDF et EDZL et avec différentes charges processeur (sur un circuit type MPC5517 et un UltraSparc T1) illustrent l’efficacité de la technique proposée. / Increasing the density of transistors in electronic circuits leads to an increase in energy consumption resulting in more complex thermal phenomena to master. For systems embedded in environments where the ambient temperature can vary in large range (e.g. automotive), these thermal effects can induce reliability problems. Among classical failure mechanisms thermal cycles (CTs) produce deformations in materials and play a major role in the cracking of the metal layers in the chip. The aim of the thesis is to propose a reduction technique of CTs suffered by the processor cores in a multiprocessor on chip architecture such that real-time application constraints are met. The example of the Freescale MPC5517 circuit has been considered. In a first step a thermal model of this circuit was developed. This was achieved from measurements taken by a thermal camera on a decapsulated circuit. Next, a simulation environment has been implemented allowing both the analysis of thermal behavior and the scheduling of tasks so as to highlight the influence of temperature on the dissipated power. A global heuristic to reduce both the CTs and the maximum temperature of processors has been studied. It takes into account variations in the ambient temperature and is based on DVFS and DPM techniques. Simulation results with global scheduling algorithms RM, EDF and EDZL and different processor loads (for a MPC5517 type circuit and a T1 UltraSparc from Sun Microsystems) illustrate the effectiveness of the proposed technique.

Der vierte Band der wissenschaftlichen Schriftenreihe Eingebettete Selbstorganisierende Systeme widmet sich der Entwicklung von Fehlermodellen für eingebettete, verteilte Multi – Prozessorsysteme. Diese werden zu einem hierarchischen Netzwerk zur Steuerung von Flugzeugen (Avionik) verbunden und mehr und mehr im Automotive Bereich eingesetzt. Hier gilt es höchste Sicherheitsstandards einzuhalten und maximale Verfügbarkeit zu garantieren. Herr Fischer integriert die Modellierung von möglichen Fehlern in den Entwurfsprozess. Auf Grundlage des π-Kalküls entwickelt Herr Fischer ein formales Fehlermodell, das eine einheitliche Modellierung von Fehlerfällen unterstützt. Dabei werden interessante Bezüge zur Bi-Simulation sowie zu Methoden des Modell Checkings hergestellt. Die theoretischen Ergebnisse werden an einem komplexen Beispiel anschaulich illustriert. So kann der Leser die Mächtigkeit des entwickelten Ansatzes nachvollziehen und wird motiviert, die entwickelte Methodik auf weitere Anwendungsfälle zu übertragen. / The 4th volume of the scientific series Eingebettete, selbstorganisierende Systeme (Embedded Self-Organized Systems) outlines the design of fault models for embedded distributed multi processor systems. These multi processor systems will be connected to a hierarchical network to control airplanes (avionics) and also be used more and more in the automotive area. Here it is essential to meet highest safety standards and to ensure the maximum of availability. Mr Fischer integrates the modelling of potential faults into the design process. Based on the pi-calculus, he develops a formal framework, which supports a standardised modelling of faults. Thereby, interesting connections to the Bi-Simulation as well as to methods of the Model checking are established. The theoretical results are depicted on a complex example. So it is possible for the reader to understand the complexity of this approach and is motivated to use the developed methodology in other applications. I am glad that Mr Fischer publishes his important research in this scientific series.

Avec l'essor des nouvelles technologies d'intégration sur silicium submicroniques, la consommation de puissance dans les systèmes sur puce multiprocesseur (MPSoC) est devenue un facteur primordial au niveau du flot de conception. La prise en considération de ce facteur clé dés les premières phases de conception, joue un rôle primordial puisqu'elle permet d'augmenter la fiabilité des composants et de réduire le temps d'arrivée sur le marché du produit final. Dans cette thèse, nous proposons une méthodologie efficace pour l'estimation de la consommation de puissance des plateformes MPSoC. Cette méthodologie repose sur une combinaison d'une analyse fonctionnelle de la puissance (FLPA) pour l'obtention des modèles de consommation et d'une technique de simulation au niveau transactionnel (TLM) pour calculer la puissance de l'ensemble du système. Fondamentalement, FLPA est proposée pour modéliser le comportement des processeurs en terme de consommation afin d'obtenir des modèles paramétrés de haut niveau. Dans ce travail, FLPA est étendue pour mettre en place des modèles de puissance génériques pour les différentes parties du système (mémoire, logique reconfigurable, etc.). En outre, un environnement de simulation a été développé au niveau transactionnel afin d'évaluer avec précision les activités utilisées dans les modèles de consommation. La combinaison de ces deux parties conduit à une estimation de la puissance hybride qui donne un meilleur compromis entre la précision et la vitesse. La méthodologie proposée a plusieurs avantages: elle estime la consommation du système embarqué dans tous ses éléments et conduit à des estimations précises sans matériel coûteux et complexe. La méthodologie proposée est évolutive pour explorer des architectures complexes embarquées. Notre outil d'estimation de puissance au niveau du système PETS (Power Estimation Tool at System-level) est développé sur la base de la méthodologie proposée. L'efficacité de notre outil PETS en termes de précision et rapidité est validée par des architectures embarquées monoprocesseur et multiprocesseur conçues autour des plateformes OMAP (3530 et 5912) et FPGA Pro Xilinx Virtex II.

Power dissipation in CMOS circuits is of growing concern as the computational requirements of portable, battery operated devices increases. The ability to easily develop application specific circuits, rather than program general-purpose architectures can provide tremendous power savings. To this end, we present a design platform for rapidly developing power efficient hardware architectures starting at a system level. This high level VLSI design platform, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time and power dissipation. We compare the CoDeL platform to a modern DSP and find that the CoDeL platform produces designs with somewhat slower run times but dramatically lower power dissipation. The CoDeL compiler produces an FSMD (Finite State Machine with Datapath) implementation of the circuit. This regular structure can be exploited to further reduce power through various techniques. To reduce dynamic power dissipation in the resulting architecture, the CoDeL compiler automatically inserts clock gating for registers. Power analysis shows that CoDeL's automated, high-level clock gating provides considerably more power savings than existing automated clock gating tools. To reduce static power, we use the CoDeL platform to analyze the potential and performance impact of power gating individual registers. We propose a static gating method, with very low area overhead, which uses the information available to the CoDeL compiler to predict, at compile time, when the registers can be powered off and powered on. Static branch prediction is used to more intelligently traverse the finite state machine description of the circuit to discover gating opportunities. Using simulation and estimation, we find that CoDeL with backward branch prediction gives the best overall combination of gating potential and performance. Compared to a dynamic time-based technique, this method gives dramatically more power savings, without any additional performance loss. Finally, we propose techniques to efficiently partition a FSMD using Integer Linear Programming and a simulated annealing approach. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve considerable power savings since only one processor is active at any given time. Implementation and estimation shows that significant power savings can be expected, when the original machine is partitioned into two or more submachines.

Abstract This thesis concentrates on evaluating and improving the throughput performances of mobile users in high speed vehicles. In particular, high speed train (HST) scenarios are considered. Emphasis is placed on practical designs and methods that take into account distinctive HST characteristics. A two-hop communication link, i.e., base station (BS)-to-HST and HST-to-onboard users (OBUs) is adopted. The main target is to improve the throughput performance on the BS-to-HST communication link, which is assumed to be the main bottleneck in the whole communication link, since the HST-to-OBU communication link is assumed to have good channel quality due to the short link distance with relatively stationary OBUs. The algorithms developed are assessed through link and system level simulations. A theoretical and practical study of the throughput maximization problem in a single and multi-cell multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) train scenario are considered with and without cooperation between train carriages. Two low-complexity transmission schemes based on simple antenna selection (AS) methods with spatial multiplexing (SM) are proposed. The simulation results demonstrate that large antenna arrays with AS and SM transmission strategies have the potential to significantly improve the throughput of the BS-to-train link in HST scenarios. Resource sharing methodologies between the moving relay nodes (MRNs) on the HST and ground macro users (GMUs) were also studied in a multi-cell MIMO-OFDM train scenario. Direct application of existing resource scheduling methods will not be appropriate to efficiently and fairly share resources, since the MRNs and the GMUs have different processing capabilities. Hence, two hybrid resource scheduling methods are analyzed in conjunction with joint and disjoint resource management. The tradeoff between the number of MRNs and receive antennas that should be installed on an HST was also examined in the context of throughput performance and capital expenditure. Results show that joint scheduling does not provide the best overall performance and there is a need to schedule each group of mobile terminals (MTs) separately. Finally, the feasibility of the use of higher frequency bands (HFBs) was examined in HST scenarios. A timer-based beam selection scheme for HST, which does not require any training time to select the appropriate beam is also proposed. The proposed beam selection scheme (PBSS) displays a close performance to the ideal singular value decomposition (SVD) scheme. / Tiivistelmä Tämä väitöskirja keskittyy mobiilikäyttäjien tiedonsiirtonopeuksien arviointiin ja parantamiseen nopeasti liikkuvissa kulkuneuvoissa. Työ käsittelee erityisesti tiedonsiirtoa suurnopeusjunissa. Työssä korostetaan käytännön menetelmiä, jotka ottavat huomioon nopeasti liikkuvien junien tiedonsiirron erityispiirteet. Työssä käytetään kahden hypyn linkkimallia, jossa tiedonsiirto kulkee tukiasemalta junaan ja junasta käyttäjälle, joka on junassa. Päätavoite on parantaa datanopeuksia tukiaseman ja junan välisessä tiedonsiirtolinkissä, jonka uskotaan olevan suurin pullonkaula koko tiedonsiirtolinkissä, koska junan ja lähes paikallaan olevan käyttäjän välinen kanava voidaan olettaa hyvälaatuiseksi linkin lyhyyden vuoksi. Kehitettyjen algoritmien suorituskykyä arvioidaan linkki- ja järjestelmätason simulaatioilla. Työssä tutkitaan tiedonsiirtonopeuden maksimointiongelmaa teoreettisella ja käytännön tasolla yhden ja usean solun MIMO OFDM junaskenaarioissa, joissa junan vaunut tekevät tai eivät tee yhteistyötä. Työssä esitetään kaksi alhaisen kompleksisuuden lähetysmenetelmää, jotka hyödyntävät yksinkertaista antennin valintamenetelmää ja tilatason multipleksointia. Simulointitulokset osoittavat, että suuret antenniryhmät, jotka hyödyntävät näitä lähetysmenetelmiä, voivat parantaa merkittävästi tiedonsiirtonopeutta tukiasemalta junaan päin. Työssä tutkitaan myös resurssien jakomenetelmiä liikkuvien junassa olevien releiden ja maatason makrokäyttäjien välillä monen solun MIMO-OFDM junaskenaariossa. Nykyisten resurssinhallintamenetelmien käyttö ei ole suoraan mahdollista tehokasta ja oikeudenmukaista resurssien jakoa, koska releillä ja makrokäyttäjillä on erilaiset prosessointikyvyt. Tämän vuoksi työssä analysoidaan kahta hybridimenetelmään resurssien skeduloinnille. Tutkimukset selventävät tasapainoa releiden lukumäärän ja junaan asennettavien vastaanotinantennien välillä tiedonsiirtonopeuden ja kustannusten osalta. Tulokset osoittavat, että yhteinen resurssien jako ei saavuta parasta suorituskykyä, eikä ole tarvetta ajoittaa jokaista matkaviestinterminaaliryhmää erikseen. Lopuksi työssä tutkitaan korkeampien taajuusalueiden soveltuvuutta tiedonsiirtoon suurnopeusjunissa. Työssä ehdotetaan ajastinpohjaista keilanvalintamenetelmää, joka ei vaadi opetusjaksoa sopivan keilan valintaan. Ehdotetun menetelmän saavuttama suorituskyky on lähellä ideaalisen singulaariarvohajotelmaa hyödyntävän menetelmän suorituskykyä.

Este estudo teve como objetivo elaborar uma proposta de indicadores para avaliação da qualidade do sistema de educação superior brasileiro e, com base nestes indicadores elaborados, medir e avaliar o desenvolvimento da sua qualidade no período 1993-2004. Considerou-se que o período escolhido está associado à intensificação do fenômeno da mercantilização da educação superior no Brasil. Para caracterizar o fenômeno, o estudo apóia-se nas perspectivas teóricas de Boaventura de Sousa Santos sobre as crises da universidade, de Ana Maria Seixas acerca das transformações privatistas e dos autores David Dill, Pedro Teixeira, Bem Jonbloed e Alberto Amaral sobre os mercados da educação superior. Os temas da qualidade e da avaliação da qualidade têm como referência principal os trabalhos de Ronald Barnett, Lee Harvey e Diana Green. Foram estudados os indicadores e sistemas de indicadores de educação adotados pelas agências internacionais, tais como Unesco e OCDE. Com essas referências foi elaborado um sistema de indicadores para avaliação do desenvolvimento da qualidade do Sesb, que compreende as categorias eqüidade, relevância, diversidade e eficácia. O estudo apresenta o sistema de indicadores elaborado e sua aplicação no período 1993-2004. Os resultados explicam a hipótese de trabalho, ou seja, em tempos de mercantilização da educação superior a qualidade da educação superior brasileira não se desenvolveu positivamente, visto que no período 1994- 2003 não foram encontradas evidências claras de melhorias do Sesb em termos de eqüidade, relevância, diversidade e eficácia. / The present study was carried out with the aiming to elaborate a proposal of indicators for assessing quality in Brazilian system for higher education and, based on those indicators, measure and evaluate the development of such quality in the period ranging from 1993 to 2004. It was considered the chosen period as associated to the increasing of the commodification of higher education in Brazil. In order to characterize that phenomena, the study used as grounds the theories developed by Boaventura de Sousa Santos, about the university crisis; by Ana Maria Seixas, about the privatizing transformations; and by David Dill, Pedro Teixeira, Bem Jonbloed, and Alberto Amaral, on the higher education markets. The matters involving quality and quality assessment have the main studies by Ronald Barnett, Lee Harvey, and Diana Green as references. The indicators and systems of education indicators adopted by international agencies such as Unesco and OCDE, were also studied. Based on those references a system of indicators for the evaluation of quality development in Sesb was elaborated, and it includes the following categories: equity, relevance, diversity, and efficiency. This study presents that indicators system as well as its application during the period 1993-2004. The results explain the hypothesis upon which work was developed, that is, in times of commodification of higher education, the quality of such education in Brazil has not developed positively. That is said based on the fact that during the period 1993-2004 there could not be found clear evidences of improvement in Sesb in what concerns equity, relevance, diversity, and efficiency.

The Internet of Things (IoT) has ushered in an age where low-power sensors generate data which are communicated to a back-end cloud for massive data computation tasks. From the hardware perspective this implies co-existence of several power-efficient sub-systems working harmoniously at the sensor nodes capable of communication and high-speed processors in the cloud back-end. The package-board system-level design plays a crucial role in determining the performance of such low-power sensors and high-speed computing and communication systems. Although there exist several commercial solutions for electromagnetic and circuit analysis and verification, problem diagnosis and design tools are lacking leading to longer design cycles and non-optimal system designs. This work aims at developing methodologies for faster analysis, sensitivity based diagnosis and multi-objective design towards signal integrity and power integrity of such package-board system layouts. The first part of this work aims at developing a methodology to enable faster and more exhaustive design space analysis. Electromagnetic analysis of packages and boards can be performed in time domain, resulting in metrics like eye-height/width and in frequency domain resulting in metrics like s-parameters and z-parameters. The generation of eye-height/width at higher bit error rates require longer bit sequences in time domain circuit simulation, which is compute-time intensive. This work explores learning based modelling techniques that rapidly map relevant frequency domain metrics like differential insertion-loss and cross-talk, to eye-height/width therefore facilitating a full-factorial design space sweep. Numerical results performed with artificial neural network as well as least square support vector machine on SATA 3.0 and PCIe Gen 3 interfaces generate less than 2% average error with order of magnitude speed-up in eye-height/width computation. Accurate power distribution network design is crucial for low-power sensors as well as a cloud sever boards that require multiple power level supplies. Achieving target power-ground noise levels for low power complex power distribution networks require several design and analysis cycles. Although various classes of analysis tools, 2.5D and 3D, are commercially available, the presence of design tools is limited. In the second part of the thesis, a frequency domain mesh-based sensitivity formulation for DC and AC impedance (z-parameters) is proposed. This formulation enables diagnosis of layout for maximum impact in achieving target specifications. This sensitivity information is also used for linear approximation of impedance profile updates for small mesh variations, enabling faster analysis. To enable designing of power delivery networks for achieving target impedance, a mesh-based decoupling capacitor sensitivity formulation is presented. Such an analytical gradient is used in gradient based optimization techniques to achieve an optimal set of decoupling capacitors with appropriate values and placement information in package/boards, for a given target impedance profile. Gradient based techniques are far less expensive than the state of the art evolutionary optimization techniques used presently for a decoupling capacitor network design. In the last part of this work, the functional similarities between package-board design and radio frequency imaging are explored. Qualitative inverse-solution methods common to the radio frequency imaging community, like Tikhonov regularization and Landweber methods are applied to solve multi-objective, multi-variable signal integrity package design problems. Consequently a novel Hierarchical Search Linear Back Projection algorithm is developed for an efficient solution in the design space using piecewise linear approximations. The presented algorithm is demonstrated to converge to the desired signal integrity specifications with minimum full wave 3D solve iterations.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-05-04T22:06:03Z No. of bitstreams: 1 HELDER FERNANDO DE ARAÚJO OLIVEIRA - TESE PPGCC 2015..pdf: 1535968 bytes, checksum: ea0ac08d16d7773542f5d7193c85c162 (MD5) / Made available in DSpace on 2018-05-04T22:06:03Z (GMT). No. of bitstreams: 1 HELDER FERNANDO DE ARAÚJO OLIVEIRA - TESE PPGCC 2015..pdf: 1535968 bytes, checksum: ea0ac08d16d7773542f5d7193c85c162 (MD5) Previous issue date: 2015-11-10 / Capes / Consumo de energia é um grande desafio durante o projeto de um SoC (System-on-a-Chip). Dependendo do projeto, para garantir maior precisão na estimação do consumo de energia, pode ser necessário estimar o consumo de energia do sistema ou parte dele utilizando diferentes elementos: diferentes abordagens de estimação, ferramentas ou, até mesmo, modelos descritos em variadas linguagens e/ou níveis de abstração. Porém, consiste em um desafio incorporar tais elementos para criação de um ambiente de simulação distribuído e heterogêneo, o qual permita que estes se comuniquem e troquem informações de modo sincronizado. Diante do exposto, a presente pesquisa tem como objetivo desenvolver uma abordagem, utilizando-se High Level Architecture (HLA), a fim de permitir a criação de um ambiente de simulação distribuído e heterogêneo, composto por diferentes ferramentas e modelos. Estes modelos podem ser descritos em diversas linguagens e/ou níveis de abstração, como também podem utilizar diferentes abordagens a estimação do consumo de energia. O uso da HLA permite que os elementos que compõem este ambiente heterogêneo possam ser simulados de maneira sincronizada e distribuída. A abordagem deve proporcionar a coleta e o agrupamento de dados de estimação de consumo de energia de modo centralizado. Para realização dos estudos de caso, foi utilizado um benchmark composto por um conjunto escalável de MPSoC (MultiProcessor System-on-Chip) descrito em C++/SystemC e o arcabouço Ptolemy. Um projeto em SystemVerilog/Verilog também foi utilizado para validar a coleta de dados de estimação de consumo de energia de modelos descritos nessas linguagens, por meio da abordagem proposta. Resultados experimentais demonstraram a flexibilidade da abordagem e sua aplicabilidade para a criação de um ambiente de simulação síncrono e heterogêneo, o qual promove uma visão integrada dos dados de energia estimados. / Energy consumption is a big challenge in SoC (System-on-a-Chip) design. Depending on the project requirements, to guarantee a better accuracy in power estimation, it might be necessary to estimate the power consumption of a system or part of it using different elements: different power estimation approaches, tools or, even, models described in different languages and/or abstraction levels. However, it is a challenge to incorporate these elements to create a simulation environment distributed and heterogeneous, which allows these elements to communicate and exchange information synchronously. In view of what has been exposed, the present research aims to develop an approach using HLA (High Level Architecture), enabling the creation of an environment distributed and heterogeneous, composed by different tools and models. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, it has been used a benchmark composed of a scalable set of MPSoCs (MultiProcessor Systemon-Chip) which is described in C++/SystemC and the Ptolemy framework. A project in SystemVerilog/Verilog was also used to validate the power estimation data collected from models described in these languages, through the proposed approach. The experimental results show the approach flexibility and its applicability on creation of a distributed and synchronous simulation environment, which promotes an integrated view of power estimation data.