General uncertainty analysis was used to evaluate the performance of a Rocket-Based Combined Cycle (RBCC) engine system. To estimate the uncertainties of test results, uncertainties of basic measurements such as temperature, pressure, mass flow rate, and thrust were determined. The desired test results of interest included specific impulse and characteristic velocity. Various possible test facilities were reviewed to obtain background information and example test run conditions. Based on the test run conditions, five methods of determining specific impulse were evaluated. Also, theoretical and actual characteristic velocities were analyzed to evaluate C* efficiency. Initially, general uncertainty analyses were completed relative to 1% accuracy for each measured variable. Then, cases were run using more realistic uncertainty estimates. The relative contributions of the different variables? uncertainties to the overall uncertainty of the selected performance parameters were also calculated. This process helps to identify the critical measurements from an uncertainty standpoint and can be a significant guide in the cost effective use of resources to reduce the test uncertainty.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Time-Space-Position-Information (TSPI) visualization systems used today at the Air Force Flight Test Center (AFFTC) and simulation visualization tools used at the Air Armament Center (AAC) utilize two-dimensional (2D) display systems for both real-time and post-mission data analysis. Examples are monitors and large screen projection systems. Some TSPI visualization systems generate three-dimensional (3D) data as output, but the 3D data is translated so that it is compatible with 2D display systems. Currently, 3D volumetric display systems are being utilized by the Federal Aviation Administration (FAA) for monitoring air traffic in 3D without 3D goggles. The aircraft’s position information is derived from radar and fed to a volumetric display. The AFFTC and AAC need a similar system for Open Air Range testing utilizing the Global Positioning System (GPS) as the source of position information and Installed Systems Testing utilizing 6 Degree of Freedom (DOF) flight simulation data as the source of position information. This system should be capable of displaying realistic terrain structures, vehicle models and physical test configurations along with text data overlays. The ability to display the mission in real-time on a volumetric 3D display makes it possible for test engineers to observe resource utilization continuously as the mission develops. Quicker turn-around times in the decision process will lead to more efficient use of limited test resources and will increase the information content of the data being collected.

Computer systems which interact with human users to collect, update or provide information are growing more complex. Additionally, users are demanding more thorough testing of all computer systems. Because of the complexity and thoroughness required, automation of interactive systems testing is desirable, especially for functional testing. Many currently available testing tools, like program proving, are impractical for testing large systems. The solution presented here is the development of an automated test system which simulates human users. This system incorporates a high-level programming language, ATLIS. ATLIS programs are compiled and interpretively executed. Programs are selected for execution by operator command, and failures are reported to the operator's console. An audit trail of all activity is provided. This solution provides improved efficiency and effectiveness over conventional testing methods.

<p>The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. These SOCs usually contain a microprocessor, several DSP cores (Digital-Signal-Processors), other hardware blocks, on-chip memories and peripherals.</p><p>As new IC process technologies are deployed, with decreasing geometrical dimensions, the probabilities of hardware faults to occur during operation are increasing. Testing SOCs is becoming a very complex issue due to the increasing complexity of the design and the increasing need of a test mechanism that is able to achieve acceptable fault coverage in a short test application time with low power consumption without the use of external logic testers.</p><p>As a part of the overall test strategy for a SOC, functional self-testing of a DSP core is considered in this project to be applied in the field. This test is used to verify whether fault indications in systems are caused by permanent hardware faults in the DSP. If so, the DSP where the fault is located needs to be taken out of operation, and the board it sits on will be later replaced. If not, the operational state can be restored, and the system will become fully functional again.</p><p>The main purpose of this project is to develop a functional self-test of a DSP core, and to evaluate the characteristics of the test. This project also involves proposing a scheme on how to apply a functional test on a DSP core in an embedded environment, and how to retrieve results from the test. The test program shall run at system speed.</p><p>To develop and measure the quality of the test program, two different coverage metrics were used. The first is the code coverage metric achieved by simulating the test program on the RTL representation of the DSP. The second metric used was the fault coverage achieved. The fault coverage of the test was calculated using a commercial Fault Simulator working on a gate-level representation of the DSP. The results achieved in this report show that this proposed approach can achieve acceptable levels of fault coverage in short execution time without the need for external testers which makes it possible to perform the self-test in the field. This approach has the unique property of not requiring any hardware modifications in the DSP design, and the ability of testing several DSPs in parallel.</p>

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This thesis presents the development of small, inexpensive unmanned aerial vehicles (UAVs) to achieve autonomous fight. Fixed wing hobby model planes are modified and instrumented to form experimental platforms. Different sensors employed to collect the flight data are discussed along with their calibrations. The time constant and delay for the servo-actuators for the platform are estimated. Two different data collection and processing units based on micro-controller and PC104 architectures are developed and discussed. These units are also used to program the identification and control algorithms. Flight control of fixed wing UAVs is a challenging task due to the coupled, time-varying, nonlinear dynamic behaviour. One of the possible alternatives for the flight control system is to use the intelligent adaptive control techniques that provide online learning capability to cope with varying dynamics and disturbances. Neural network based indirect adaptive control strategy is applied for the current work. The two main components of the adaptive control technique are the identification block and the control block. Identification provides a mathematical model for the controller to adapt to varying dynamics. Neural network based identification provides a black-box identification technique wherein a suitable network provides prediction capability based upon the past inputs and outputs. Auto-regressive neural networks are employed for this to ensure good retention capabilities for the model that uses the past outputs and inputs along with the present inputs. Online and offline identification of UAV platforms are discussed based upon the flight data. Suitable modifications to the Levenberg-Marquardt training algorithm for online training are proposed. The effect of varying the different network parameters on the performance of the network are numerically tested out. A new performance index is proposed that is shown to improve the accuracy of prediction and also reduces the training time for these networks. The identification algorithms are validated both numerically and flight tested. A hardware-in-loop simulation system has been developed to test the identification and control algorithms before flight testing to identify the problems in real time implementation on the UAVs. This is developed to keep the validation process simple and a graphical user interface is provided to visualise the UAV flight during simulations. A dual neural network controller is proposed as the adaptive controller based upon the identification models. This has two neural networks collated together. One of the neural networks is trained online to adapt to changes in the dynamics. Two feedback loops are provided as part of the overall structure that is seen to improve the accuracy. Proofs for stability analysis in the form of convergence of the identifier and controller networks based on Lyapunov's technique are presented. In this analysis suitable bounds on the rate of learning for the networks are imposed. Numerical results are presented to validate the adaptive controller for single-input single-output as well as multi-input multi-output subsystems of the UAV. Real time validation results and various flight test results confirm the feasibility of the proposed adaptive technique as a reliable tool to achieve autonomous flight. The comparison of the proposed technique with a baseline gain scheduled controller both in numerical simulations as well as test flights bring out the salient adaptive feature of the proposed technique to the time-varying, nonlinear dynamics of the UAV platforms under different flying conditions.

No description available.

Doctorat en sciences psychologiques / info:eu-repo/semantics/nonPublished

The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. These SOCs usually contain a microprocessor, several DSP cores (Digital-Signal-Processors), other hardware blocks, on-chip memories and peripherals. As new IC process technologies are deployed, with decreasing geometrical dimensions, the probabilities of hardware faults to occur during operation are increasing. Testing SOCs is becoming a very complex issue due to the increasing complexity of the design and the increasing need of a test mechanism that is able to achieve acceptable fault coverage in a short test application time with low power consumption without the use of external logic testers. As a part of the overall test strategy for a SOC, functional self-testing of a DSP core is considered in this project to be applied in the field. This test is used to verify whether fault indications in systems are caused by permanent hardware faults in the DSP. If so, the DSP where the fault is located needs to be taken out of operation, and the board it sits on will be later replaced. If not, the operational state can be restored, and the system will become fully functional again. The main purpose of this project is to develop a functional self-test of a DSP core, and to evaluate the characteristics of the test. This project also involves proposing a scheme on how to apply a functional test on a DSP core in an embedded environment, and how to retrieve results from the test. The test program shall run at system speed. To develop and measure the quality of the test program, two different coverage metrics were used. The first is the code coverage metric achieved by simulating the test program on the RTL representation of the DSP. The second metric used was the fault coverage achieved. The fault coverage of the test was calculated using a commercial Fault Simulator working on a gate-level representation of the DSP. The results achieved in this report show that this proposed approach can achieve acceptable levels of fault coverage in short execution time without the need for external testers which makes it possible to perform the self-test in the field. This approach has the unique property of not requiring any hardware modifications in the DSP design, and the ability of testing several DSPs in parallel.

Very small aperture terminal (VSAT) networks offer a solution to the increasing demand for low-density voice and data communications. Spread Spectrum and single-channel-per-carrier (SCPC) transmission techniques work well for multiple access purposes while allowing the earth station antennas to remain small. Direct sequence code division multiple access (DS-CDMA) is the simplest spread spectrum technique to use in a VSAT network, since a frequency synthesizer is not required for each terminal. This thesis examines DS-CDMA and SCPC Ku-band VSAT satellite systems for low-density (64 kbps or less) communications. It develops methods for calculating PN coding cross-correlation interference losses and satellite transponder effects, and it includes these losses in a performance analysis of 50 channel full mesh and star network architectures. It demonstrates selection of operating conditions producing optimum performance. / Master of Science