¡@¡@Because of the poly-si thin film transistor have the advantage of high mobility, it can improve the analysis for the flat plan display. Using the above advantage can combine the integrated circuit as control IC and memory on the small panel to reduce the number between the switch circuits and the outside contacts. These precise circuits must be considering the photo current¡Bthermal effects and the parasitical capacitance more due to the influence of these precise circuits is more serious than the switch circuits. In my thesis, the research of the electrical characteristics of the newest excimer laser crystallize coplane poly-si thin film transistors ,and using the device length with width is 128um/6um and 128um/16um can be extracted that the environment of the facing illumination have the photo-leakage current than none illumination about four orders, and the photo-leakage current is not consider with any gate voltage. ¡@¡@With the discussion of the capacitance, the main point of my researches is to change different conditions to extract the gate to source capacitance (Cgs). In addition, the slight carriers may effect the devices with the high mobility system on panel (SOP) technology error, the temperature must be considered. ¡@¡@We find the mobility is bigger at the environment of the temperature is 300K than the environment of the temperature is 100K when the device work in the linear region and the on current is lower at the environment of the temperature is 300K than the environment of the temperature is 100K when the device work in the saturation region. Using some references and some models as the concepts can analysis some phenomenons I refer to above.

A novel polymer semiconductor with side chains thermally cleavable at a low temperature of 200 °C was synthesized. The complete cleavage and removal of the insulating 2-octyldodecanoyl side chains were verified with TGA, FT-IR, and NMR data. The N-H groups on the native polymer backbone are expected to form intermolecular hydrogen bonds with the C=O groups on the neighboring polymer chains to establish 3-D charge transport networks. The resulting side chain-free conjugated polymer is proven to be an active p-type semiconductor material for organic thin film transistors (OTFTs), exhibiting hole mobility of up to 0.078 cm2V-1s-1. This thermo-cleavable polymer was blended with PDQT to form films that showed a higher performance than the pure individual polymers in OTFTs. MoO3 or NPB was used as a hole injection buffer layer between the metal electrodes and the polymer semiconductor film layer in OTFT devices. This buffer layer improved hole injection, while its use in the OTFT, improved the field-effect mobility significantly due to better matched energy levels between the electrodes and the polymer semiconductor.

The objective of this research was to perform a systematic investigation of the unique structural and electrical properties of epitaxial graphene at the nanoscale. As the semiconductor industry faces increasing challenges in the production of integrated circuits, due to process complexity and scaling limitations, new materials research has come to the forefront of both science and engineering disciplines. Graphene, an atomically-thin sheet of carbon, was examined as a material which may replace or become integrated with silicon nanoelectronics. Specifically, this research was focused on epitaxial graphene produced on silicon carbide. This material system, as opposed to other types of graphene, holds great promise for large-scale manufacturing, and is therefore of wide interest to the academic and industrial community. In this work, high-quality epitaxial graphene production was optimized, followed by the process development necessary to fabricate epitaxial graphene nanoribbon transistors for electrical characterization. The structural and electrical transport properties of the nanoribbons were elucidated through a series of distinct experiments. First, the size-dependent conductivity of epitaxial graphene at the nanoscale was investigated. Next, the alleviation of the detrimental effects revealed during the size-dependent conductivity study was achieved through the selective functionalization of graphene with hydrogen. Finally, two techniques were developed to allow for the complementary doping of epitaxial graphene. All of the experiments presented herein reveal new and important aspects of epitaxial graphene at the nanoscale that must be considered if the material is to be adopted for use by the semiconductor industry.

Thin film transistor (TFT) backplanes are being continuously researched for new applications such as active-matrix organic light emitting diode (AMOLED) displays, sensors, and x-ray imagers. However, the circuits implemented in presently available fabrication technologies including poly silicon (poly-Si), hydrogenated amorphous silicon (a-Si:H), and organic semiconductor, are prone to spatial and/or temporal non-uniformities. While current-programmed active matrix (AM) can tolerate mismatches and non-uniformity caused by aging, the long settling time is a significant limitation. Consequently, acceleration schemes are needed and are proposed to reduce the settling time to 20 µs. This technique is used in the development of a pixel circuit and system for biomedical imager and sensor. Here, a metal-insulator-semiconductor (MIS) capacitor is adopted for adjustment and boost of the circuit gain. Thus, the new pixel architecture supports multi-modality imaging for a wide range of applications with various input signal intensities. Also, for applications with lower current levels, a fast current-mode line driver is developed based on positive feedback which controls the effect of the parasitic capacitance. The measured settling time of a conventional current source is around 2 ms for a 100-nA input current and 200-pF parasitic capacitance whereas it is less than 4 μs for the driver presented here. For displays needed in mobile devices such as cell phones and DVD players, another new driving scheme is devised that provides for a high temporal stability, low-power consumption, high tolerance of temperature variations, and high resolution. The performance of the new driving scheme is demonstrated in a 9-inch fabricated display intended for DVD players. Also, a multi-modal imager pixel circuit is developed using this technique to provide for gain-adjustment capability. Here, the readout operation is not destructive, enabling the use of low-cost readout circuitry and noise reduction techniques. In addition, a highly stable and reliable driving scheme, based on step calibration is introduced for high precision displays and imagers. This scheme takes advantage of the slow aging of the electronics in the backplane to simplify the drive electronics. The other attractive features of this newly developed driving scheme are its simplicity, low-power consumption, and fast programming critical for implementation of large-area and high-resolution active matrix arrays for high precision.

Hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) has been used in active matrix liquid crystal displays (LCDs) and medical x-ray imagers, in which the TFT acts as pixel switches. However, instability of a-Si:H TFT is a major issue in applications where TFTs are also required to function as analogue circuit elements, such as in emerging organic light emitting diode (OLED) displays. It is known that a-Si:H TFT shows drain current degradation under electrical operation, due to two instability mechanisms: (i) defect creation in the a-Si:H active layer, and (ii) charge trapping in the gate dielectric. Nanocrystalline silicon (nc-Si) TFT has been proposed as a high performance alternative. Therefore, this thesis focuses on the design of nc-Si TFT and its outstanding issues, in the industry standard bottom-gate structure. The key for obtaining a stable TFT lies in developing a highly crystalline nc-Si active layer, without the so-called amorphous incubation layer. Therefore, processing of nc-Si by plasma enhanced chemical vapor deposition (PECVD) is studied and PECVD parameters are optimized. It is shown that very thin (15 nm) layers with crystallinity of around 60% can be obtained. Moreover, it is possible to eliminate the amorphous incubation layer, as transmission electron microscope (TEM) images showed that crystalline grains start growing immediately upon deposition at the gate dielectric interface. The nc-Si TFT reported in this work advances the state-of-the-art, by demonstrating that defect state creation is absent in the nc-Si active layer, which is deduced by performing several characterization techniques. In addition, with the proper design of the nitride gate dielectric, i.e. by using a nitrogen-rich nitride, the charge trapping instability can be minimized. Thus, it is shown that the nc-Si TFT is much more stable than the a-Si:H counterpart. Another issue with nc-Si TFT is its high drain leakage current, i.e. off-current. It is shown that off-current is determined by the conductivity of nc-Si active layer, and also affected by the quality of the silicon/passivation nitride interface. The off-current can be minimized by using a bi-layer structure so that a thin (15 nm) nc-Si is capped with a thin (35nm) a-Si:H, and values as low as 0.1 pA can be obtained. The low off-current along with superior stability of nc-Si TFT, coupled with its fabrication in the industry standard 13.56 MHz PECVD system, make it very attractive for large area applications such as pixel drivers in active matrix OLED displays and x-ray imagers.

Thin film transistors (TFTs) have brought prominent growth in both variety and utility of large area electronics market over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have attracted attention recently, due to high-performance and low-cost, as an alternative of amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs. The nc-Si:H TFTs has higher carrier mobility and better device stability than a-Si:H TFTs while lower manufacturing cost than poly-Si TFTs. However, current nc-Si:TFTs have several challenging issues on materials and devices, on which this thesis focuses. In the material study, the gate quality silicon nitride (a-SiNx) films and doped nc-Si:H contacts based on conventional plasma enhanced chemical vapor deposition (PECVD) are investigated. The feasibility of a-SiNx on TFT application is discussed with current-voltage (I-V)/capacitance-voltage(C-V) measurement and Fourier Transform Infrared Spectroscopy (FTIR) results which demonstrate 4.3 MV/cm, relative permittivity of 6.15 and nitrogen rich composition. The doped nc-Si:H for contact layer of TFTs is characterized with Raman Spectroscopy and I-V measurements to reveal 56 % of crystalinity and 0.42 S/cm of dark conductivity. Inverted staggered TFT structure is fabricated for nc-Si:H TFT device research using fully wet etch fabrication process which requires five lithography steps. The process steps are described in detail as well as adaptation of the fabrication process to a backplane fabrication for direct conversion X-ray imagers. The modification of TFT process for backplane fabrication involves two more lithography steps for mushroom electrode formation while other pixel components is incorporated into the five lithography step TFT process. The TFTs are electrically characterized demonstrating 7.22 V of threshold voltage, 0.63 S/decade of subthreshold slope, 0.07 cm2/V•s of field effect mobility, and 106 of on/off ratio. The transfer characteristics of TFTs reveal a severe effect of parasitic resistance which is induced from channel layer itself, a contact between channel layer and doped nc-Si:H contact layer, the resistance of doped nc-Si:H contact layer, and a contact between the doped nc-Si:H layer and source/drain metal electrodes. The parasitic resistance effect is investigated using numerical simulation method by various parasitic resistances, channel length of the TFT, and intrinsic properties of nc-Si:H channel layer. It reveals the parasitic resistance effect become severe when the channel is short and has better quality, therefore, several further research topics on improving contact nc-Si:H quality and process adjustment are required.

Thin film transistor (TFT) backplanes are being continuously researched for new applications such as active-matrix organic light emitting diode (AMOLED) displays, sensors, and x-ray imagers. However, the circuits implemented in presently available fabrication technologies including poly silicon (poly-Si), hydrogenated amorphous silicon (a-Si:H), and organic semiconductor, are prone to spatial and/or temporal non-uniformities. While current-programmed active matrix (AM) can tolerate mismatches and non-uniformity caused by aging, the long settling time is a significant limitation. Consequently, acceleration schemes are needed and are proposed to reduce the settling time to 20 µs. This technique is used in the development of a pixel circuit and system for biomedical imager and sensor. Here, a metal-insulator-semiconductor (MIS) capacitor is adopted for adjustment and boost of the circuit gain. Thus, the new pixel architecture supports multi-modality imaging for a wide range of applications with various input signal intensities. Also, for applications with lower current levels, a fast current-mode line driver is developed based on positive feedback which controls the effect of the parasitic capacitance. The measured settling time of a conventional current source is around 2 ms for a 100-nA input current and 200-pF parasitic capacitance whereas it is less than 4 μs for the driver presented here. For displays needed in mobile devices such as cell phones and DVD players, another new driving scheme is devised that provides for a high temporal stability, low-power consumption, high tolerance of temperature variations, and high resolution. The performance of the new driving scheme is demonstrated in a 9-inch fabricated display intended for DVD players. Also, a multi-modal imager pixel circuit is developed using this technique to provide for gain-adjustment capability. Here, the readout operation is not destructive, enabling the use of low-cost readout circuitry and noise reduction techniques. In addition, a highly stable and reliable driving scheme, based on step calibration is introduced for high precision displays and imagers. This scheme takes advantage of the slow aging of the electronics in the backplane to simplify the drive electronics. The other attractive features of this newly developed driving scheme are its simplicity, low-power consumption, and fast programming critical for implementation of large-area and high-resolution active matrix arrays for high precision.

Hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) has been used in active matrix liquid crystal displays (LCDs) and medical x-ray imagers, in which the TFT acts as pixel switches. However, instability of a-Si:H TFT is a major issue in applications where TFTs are also required to function as analogue circuit elements, such as in emerging organic light emitting diode (OLED) displays. It is known that a-Si:H TFT shows drain current degradation under electrical operation, due to two instability mechanisms: (i) defect creation in the a-Si:H active layer, and (ii) charge trapping in the gate dielectric. Nanocrystalline silicon (nc-Si) TFT has been proposed as a high performance alternative. Therefore, this thesis focuses on the design of nc-Si TFT and its outstanding issues, in the industry standard bottom-gate structure. The key for obtaining a stable TFT lies in developing a highly crystalline nc-Si active layer, without the so-called amorphous incubation layer. Therefore, processing of nc-Si by plasma enhanced chemical vapor deposition (PECVD) is studied and PECVD parameters are optimized. It is shown that very thin (15 nm) layers with crystallinity of around 60% can be obtained. Moreover, it is possible to eliminate the amorphous incubation layer, as transmission electron microscope (TEM) images showed that crystalline grains start growing immediately upon deposition at the gate dielectric interface. The nc-Si TFT reported in this work advances the state-of-the-art, by demonstrating that defect state creation is absent in the nc-Si active layer, which is deduced by performing several characterization techniques. In addition, with the proper design of the nitride gate dielectric, i.e. by using a nitrogen-rich nitride, the charge trapping instability can be minimized. Thus, it is shown that the nc-Si TFT is much more stable than the a-Si:H counterpart. Another issue with nc-Si TFT is its high drain leakage current, i.e. off-current. It is shown that off-current is determined by the conductivity of nc-Si active layer, and also affected by the quality of the silicon/passivation nitride interface. The off-current can be minimized by using a bi-layer structure so that a thin (15 nm) nc-Si is capped with a thin (35nm) a-Si:H, and values as low as 0.1 pA can be obtained. The low off-current along with superior stability of nc-Si TFT, coupled with its fabrication in the industry standard 13.56 MHz PECVD system, make it very attractive for large area applications such as pixel drivers in active matrix OLED displays and x-ray imagers.

Thin film transistors (TFTs) have brought prominent growth in both variety and utility of large area electronics market over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have attracted attention recently, due to high-performance and low-cost, as an alternative of amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs. The nc-Si:H TFTs has higher carrier mobility and better device stability than a-Si:H TFTs while lower manufacturing cost than poly-Si TFTs. However, current nc-Si:TFTs have several challenging issues on materials and devices, on which this thesis focuses. In the material study, the gate quality silicon nitride (a-SiNx) films and doped nc-Si:H contacts based on conventional plasma enhanced chemical vapor deposition (PECVD) are investigated. The feasibility of a-SiNx on TFT application is discussed with current-voltage (I-V)/capacitance-voltage(C-V) measurement and Fourier Transform Infrared Spectroscopy (FTIR) results which demonstrate 4.3 MV/cm, relative permittivity of 6.15 and nitrogen rich composition. The doped nc-Si:H for contact layer of TFTs is characterized with Raman Spectroscopy and I-V measurements to reveal 56 % of crystalinity and 0.42 S/cm of dark conductivity. Inverted staggered TFT structure is fabricated for nc-Si:H TFT device research using fully wet etch fabrication process which requires five lithography steps. The process steps are described in detail as well as adaptation of the fabrication process to a backplane fabrication for direct conversion X-ray imagers. The modification of TFT process for backplane fabrication involves two more lithography steps for mushroom electrode formation while other pixel components is incorporated into the five lithography step TFT process. The TFTs are electrically characterized demonstrating 7.22 V of threshold voltage, 0.63 S/decade of subthreshold slope, 0.07 cm2/V•s of field effect mobility, and 106 of on/off ratio. The transfer characteristics of TFTs reveal a severe effect of parasitic resistance which is induced from channel layer itself, a contact between channel layer and doped nc-Si:H contact layer, the resistance of doped nc-Si:H contact layer, and a contact between the doped nc-Si:H layer and source/drain metal electrodes. The parasitic resistance effect is investigated using numerical simulation method by various parasitic resistances, channel length of the TFT, and intrinsic properties of nc-Si:H channel layer. It reveals the parasitic resistance effect become severe when the channel is short and has better quality, therefore, several further research topics on improving contact nc-Si:H quality and process adjustment are required.

In this thesis, I will present the experimental results of the dynamics of superconducting single electron transistors (sSETs), under the influence of tunable dissipation. The sSET, consisting of two dc SQUIDs in series and the third gate electrode, is deposited onto a GaAs/AlGaAs heterostructure which contains a two dimensional electron gas plane 100nm beneath the substrate surface. The Josephson coupling energy, charging energy and dissipation related Hamiltonian can all be tuned in situ, while keeping others unchanged. We measured the switching current statistics and the transport properties, as a function of the dissipation and gate charge at different temperatures. If the sSET is in the classical regime where phase is a good quantum variable, we found that the switching current and corresponding Josephson energy decrease as dissipation increases. Our observation agrees qualitatively with the theoretical calculation of a single Josephson junction with dominant Josephson energy, in a frequency dependent dissipative environment where energy barrier decreases as dissipation increases in thermally activated escape regime. This dissipation dependence result can be understood as the consequence of a reduced quantum fluctuations in the charge numbers. Whereas in the charging regime, the switching current shows a 1e periodicity with respect to gate charge, indicating a pronounced charging effect. At a specific gate charge number, quantum fluctuations of the phase variable are compressed as dissipation increases, resulting in an enhanced switching current and Josephson energy. This result matches the theory of a sSET capacitively coupled to a dissipative environment qualitatively. The temperature dependence of the switching current histogram indicates the existence of both quantum and classical thermal phase diffusion. Moreover, quantum charge fluctuations are minimized at the degeneracy point, causing a sharp dip on the width of the switching current histogram. For a sSET with comparable Josephson energy and charging energy, quantum fluctuations of both phase and charge variables are significant. The influence of dissipation on the dynamics of the device is distinct in the classical and charging regimes. Dissipation compresses quantum phase fluctuations in the charging regime, whereas reduces the quantum charge fluctuations in the classical regime. The transition between these two regimes is found to be determined by the tunnel resistance of the SQUID. The competition between Josephson and charging energies, however, is not the intrinsic parameter of this transition. Our results imply that a detailed theoretical calculation of a sSET with comparable Josephson coupling energy and charging energy under the influence of dissipation is needed.