A study is hereby presented on system embedded photonic interconnect technologies, which would address the communications bottleneck in modern exascale data centre systems driven by exponentially rising consumption of digital information and the associated complexity of intra-data centre network management along with dwindling data storage capacities. It is proposed that this bottleneck be addressed by adopting within the system electro-optical printed circuit boards (OPCBs), on which conventional electrical layers provide power distribution and static or low speed signaling, but high speed signals are conveyed by optical channels on separate embedded optical layers. One crucial prerequisite towards adopting OPCBs in modern data storage and switch systems is a reliable method of optically connecting peripheral cards and devices within the system to an OPCB backplane or motherboard in a pluggable manner. However the large mechanical misalignment tolerances between connecting cards and devices inherent to such systems are contrasted by the small sizes of optical waveguides required to support optical communication at the speeds defined by prevailing communication protocols. An innovative approach is therefore required to decouple the contrasting mechanical tolerances in the electrical and optical domains in the system in order to enable reliable pluggable optical connectivity. This thesis presents the design, development and characterisation of a suite of new optical waveguide connector interface solutions for electro-optical printed circuit boards (OPCBs) based on embedded planar polymer waveguides and planar glass waveguides. The technologies described include waveguide receptacles allowing parallel fibre connectors to be connected directly to OPCB embedded planar waveguides and board-to-board connectors with embedded parallel optical transceivers allowing daughtercards to be orthogonally connected to an OPCB backplane. For OPCBs based on embedded planar polymer waveguides and embedded planar glass waveguides, a complete demonstration platform was designed and developed to evaluate the connector interfaces and the associated embedded optical interconnect. Furthermore a large portfolio of intellectual property comprising 19 patents and patent applications was generated during the course of this study, spanning the field of OPCBs, optical waveguides, optical connectors, optical assembly and system embedded optical interconnects.

Ching Ngai-hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 81-83). / Abstracts in English and Chinese. / Chapter CHAPTER 1 ´ؤ --- INTRODUCTION --- p.1 / Chapter 1.1 --- Background on Micro Power Supply --- p.1 / Chapter 1.2 --- Literature Survey --- p.3 / Chapter 1.2.1 --- Comparison Among Different Power Sources & Transduction Mechanisms --- p.3 / Chapter 1.2.2 --- Previous Works in Vibration Based Generator --- p.6 / Chapter CHAPTER 2 一 --- DESIGN OF THE MICRO-POWER GENERATOR --- p.8 / Chapter 2.1 --- Concept of Power Generation --- p.8 / Chapter 2.2 --- Design Objectives of the Micro Power Generation --- p.9 / Chapter 2.3 --- System Modelling and Configuration of the Generator --- p.10 / Chapter 2.4 --- RESONATING STRUCTURE --- p.13 / Chapter 2.4.1 --- Material Selection --- p.13 / Chapter 2.4.2 --- Fabrication Method --- p.14 / Chapter CHAPTER 3 一 --- INDUCTING STRUCTURE --- p.17 / Chapter 3.1 --- Selection of Winding Method --- p.17 / Chapter 3.2 --- Solenoid Windings --- p.19 / Chapter 3.2.1 --- Fabrication Process --- p.19 / Chapter 3.3 --- PCB Windings --- p.20 / Chapter 3.3.1 --- Fabrication Process of the Prototype of Six-layer PCB --- p.21 / Chapter CHAPTER 4 一 --- EXPERIMENTAL RESULTS --- p.27 / Chapter 4.1 --- Experimental Setup --- p.27 / Chapter 4.1.1 --- Generator Systems --- p.27 / Chapter 4.1.2 --- Measurement of Vibration and Output from the Generator --- p.28 / Chapter 4.1.3 --- Observations of Vibration Motions --- p.31 / Chapter 4.2 --- SPRING FOR THE MICRO GENERATOR --- p.32 / Chapter 4.2.1 --- Spring Micromachining Optimization --- p.32 / Chapter 4.2.2 --- Mode Shapes and Spiral-spring Structures --- p.35 / Chapter 4.3 --- MAGNET FOR THE MICRO GENEARTOR --- p.37 / Chapter 4.3.1 --- Generator Output and Magnetic Dipole Orientation --- p.37 / Chapter 4.4 --- HAND-WIRED COIL GENEARTOR --- p.45 / Chapter 4.4.1 --- Performance of Different Design of Housings --- p.45 / Chapter 4.5 --- PCB COIL GENERATOR --- p.48 / Chapter 4.5.1 --- Size of PCB Coils vs. Generator Output --- p.48 / Chapter 4.5.2 --- Effect of Number of PCB Layers --- p.54 / Chapter 4.5.3 --- Array of Generators --- p.61 / Chapter CHAPTER 5 一 --- MODELLING AND COMPUTER SIMULATION --- p.63 / Chapter 5.1 --- Modelling the Second-Order System --- p.63 / Chapter CHAPTER 6 一 --- APPLICATION DEMONSTRATIONS --- p.69 / Chapter 6.1 --- INFRARED SIGNAL TRANSMISSION --- p.69 / Chapter 6.2 --- RF WIRELESS TEMPERATURE SENSING SYSTEM --- p.70 / Chapter CHAPTER 7 ´ؤ --- CONCLUSION --- p.75 / Chapter CHAPTER 8 一 --- FUTURE WORK --- p.77 / BIBLIOGRAPHY --- p.81 / APPENDIX --- p.84

Tan Xuesong. / "June 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (p. 247-251). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan. / We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning. / Sham Chiu Wing. / "March 2006." / Adviser: Young Fung Yu. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 106-115). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Lai Tsz Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 123-129). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.4 / Chapter 1.3 --- Floorplanning --- p.7 / Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11 / Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13 / Chapter 1.4 --- Motivations and Contributions --- p.17 / Chapter 1.5 --- Organization of this Thesis --- p.18 / Chapter 2 --- Literature Review on Floorplan Representation --- p.20 / Chapter 2.1 --- Slicing Floorplan Representation --- p.20 / Chapter 2.1.1 --- Normalized Polish Expression --- p.20 / Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21 / Chapter 2.2.1 --- Sequence Pair (SP) --- p.21 / Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23 / Chapter 2.2.3 --- O-tree --- p.25 / Chapter 2.2.4 --- B*-tree --- p.26 / Chapter 2.3 --- Mosaic Floorplan Representations --- p.28 / Chapter 2.3.1 --- Corner Block List (CBL) --- p.28 / Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31 / Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32 / Chapter 2.4 --- Summary --- p.34 / Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37 / Chapter 3.1 --- Wirelength Estimation --- p.37 / Chapter 3.2 --- Congestion Optimization --- p.38 / Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41 / Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43 / Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44 / Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46 / Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48 / Chapter 3.3 --- Buffer Planning --- p.49 / Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51 / Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55 / Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58 / Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60 / Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60 / Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62 / Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63 / Chapter 3.4 --- Summary --- p.66 / Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68 / Chapter 4.1 --- Introduction --- p.68 / Chapter 4.2 --- Overview of Our Floorplanner --- p.70 / Chapter 4.3 --- Wire Density Model --- p.71 / Chapter 4.3.1 --- Computation of Ni --- p.72 / Chapter 4.3.2 --- Computation of Pi --- p.74 / Chapter 4.3.3 --- Usage of Mirror TBT --- p.76 / Chapter 4.4 --- Implementation --- p.76 / Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76 / Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81 / Chapter 4.4.3 --- Cost Function --- p.81 / Chapter 4.4.4 --- Complexity --- p.81 / Chapter 4.5 --- Experimental Results --- p.82 / Chapter 4.6 --- Conclusion --- p.83 / Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85 / Chapter 5.1 --- Introduction --- p.85 / Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87 / Chapter 5.3 --- Overview of Our Floorplanner --- p.88 / Chapter 5.4 --- Buffer Planning --- p.89 / Chapter 5.4.1 --- Feasible Grids --- p.89 / Chapter 5.4.2 --- Table Look-up Approach --- p.89 / Chapter 5.5 --- Implementation --- p.91 / Chapter 5.5.1 --- Building the Look-up Tables --- p.91 / Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94 / Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101 / Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105 / Chapter 5.5.5 --- I/O Pin Locations --- p.106 / Chapter 5.5.6 --- Cost Function --- p.110 / Chapter 5.5.7 --- Complexity --- p.111 / Chapter 5.6 --- Experimental Results --- p.112 / Chapter 5.6.1 --- Selected Value for A --- p.112 / Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113 / Chapter 5.7 --- Conclusion --- p.116 / Chapter 6 --- Conclusion --- p.118 / Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120 / Bibliography --- p.123

Advances in semiconductor technology and design automation methods have introduced a new era for electronic products. With design sizes in millions of logic gates and operating frequencies in GHz, defects-per-million rates continue to increase, and defects are manifesting themselves in subtle ways. / Diagnosing functional failures in complicated electronic boards is a challenging task, wherein debug technicians try to identify defective components by analyzing some syndromes obtained from the application of diagnostic tests. The diagnosis effectiveness and efficiency rely heavily on the quality of the in-house developed diagnostic tests and the debug technicians’ knowledge and experience, which, however, have no guarantees nowadays. To tackle this problem, this thesis proposes a novel agent-assisted diagnostic framework for board-level functional failures, namely AgentDiag, which facilitates to evaluate the quality of the diagnostic tests and bridge the knowledge gap between the diagnostic programmers who write diagnostic tests and the debug technicians who conduct in-field diagnosis with a lightweight model of the boards and tests. / Machine learning algorithms have been advocated for automated diagnosis of board-level functional failures due to the extreme complexity of the problem. Such reasoning-based solutions, however, remain ineffective at the early stage of the product cycle, simply because there are insufficient historical data for training the diagnostic system that has a large number of test syndromes. Guided by a proposed metric isolation capability, AgentDiag is able to leverage the knowledge from the lightweight model to selecting a reduced test syndrome set for diagnosis in an adaptive manner. / While AgentDiag is effective to improve the diagnostic accuracy, this technique, by excluding some test syndromes, may cause information loss for diagnosis. The thesis further presents a novel test syndrome merging methodology to address this problem. That is, by leveraging the domain knowledge of the diagnostic tests and the board structural information, we adaptively reduce the feature size of the diagnostic system by selectively merging test syndromes such that it can effectively utilize the available training cases. / Experimental results on real industrial boards and an OpenRISC design demonstrate the effectiveness of the proposed solutions. / 半導體技術和設計自動化的高速發展開啟了電子產品的新紀元。百萬級別的設計尺寸和上G赫茲的操作頻率使得每百萬次採樣數的缺陷率繼續上升，缺陷顯現方式也日益微妙。 / 複雜電子板的診斷是一項極具挑戰的工作。調試人員通常通過分析診斷測試所產生的症狀，甄別有缺陷的元件。診斷的有效性和效率就極大地依賴於診斷測試的質量和調試人員的知識經驗，但是現在這些都是沒有確定性的。為了解決這一問題，本文提出一個新穎的針對板級功能性故障的代理輔助診斷系統AgentDiag。它幫助評估診斷測試的質量，並架起編寫診斷測試的測試程式員和從事實際診斷工作的調試人員之間的橋樑。 / 因為板級診斷的極度複雜，機器學習算法已經被提出來解決這一問題。但是這些基於推導的方法在早期很難達到好的效果，原因是過大的測試數量和相對較少的訓練數據。在度量Isolation Capability的引導下，能夠適應性地利用來自輕量級模型的知識去選取一個症狀集進行診斷。 / AgentDiag可以有效地提高診斷準確率，但是由於是直接剔除一部分測試症狀，所以有可能造成信息的丟失。本文進一步提出了一個測試症狀合併的方法來解決這一問題。那就是利用診斷測試和電路板的結構描述，我們可以適應性地利用選擇性合併的測試症狀來減少測試症狀的數目，從而有效地利用已有的測試數據。 / 來自實際的工業電路板和OpenRisc設計的實驗數據驗證了提出的方法的有效性。 / Sun, Zelong. / Thesis M.Phil. Chinese University of Hong Kong 2014. / Includes bibliographical references (leaves 47-51). / Abstracts also in Chinese. / Title from PDF title page (viewed on 12, October, 2016). / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only.

Ma, Tilen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 98-100). / Abstracts in English and Chinese. / Abstract --- p.i / Chapter 0.1 --- Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design Cycle --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.11 / Chapter 1.4 --- Organization of the Thesis --- p.13 / Chapter 2 --- Literature Review on Placement Constraints in Floorplanning --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- Algorithms for Abutment Constraint --- p.16 / Chapter 2.3 --- Algorithms for Alignment Constraint --- p.18 / Chapter 2.4 --- Algorithms for Boundary Constraint --- p.20 / Chapter 2.5 --- Unified Approach for Placement Constraints --- p.23 / Chapter 2.5.1 --- Representation of Placement Constraints --- p.23 / Chapter 2.5.2 --- Handling Relative Placement Constraints --- p.24 / Chapter 2.5.3 --- Examples for Handling Placement Constraints --- p.25 / Chapter 3 --- Literature Review on Bus-Driven Floorplanning --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Previous Work --- p.28 / Chapter 3.2.1 --- Zero-Bend Bus-Driven Floorplanning [3] --- p.28 / Chapter 3.2.2 --- Two-Bend Bus-Driven Floorplanning [1] --- p.32 / Chapter 4 --- Placement Constraints for Multi-Bend Bus in TCGs --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Transitive Closure Graph [6] --- p.39 / Chapter 4.3 --- Placement Constraints for Zero-Bend Bus --- p.41 / Chapter 4.4 --- Placement Constraints for Multi-Bend Bus --- p.44 / Chapter 4.5 --- Placement Constraints for Bus Ordering --- p.45 / Chapter 4.5.1 --- Natural Bus Ordering in TCGs --- p.45 / Chapter 4.5.2 --- Explicit Bus Ordering in TCGs --- p.46 / Chapter 5 --- TCG-Based Bus-Driven Floorplanning --- p.48 / Chapter 5.1 --- Motivation --- p.48 / Chapter 5.2 --- Problem Formulation --- p.49 / Chapter 5.3 --- Methodology --- p.50 / Chapter 5.3.1 --- Construction of Reduced Graphs --- p.51 / Chapter 5.3.2 --- Construction of Common Graph --- p.52 / Chapter 5.3.3 --- Spanning Tree for Bus Assignment --- p.53 / Chapter 5.3.4 --- Formation of Bus Components --- p.55 / Chapter 5.3.5 --- Bus Feasibility Check --- p.56 / Chapter 5.3.6 --- Overlap Removal --- p.57 / Chapter 5.3.7 --- Floorplan Realization --- p.58 / Chapter 5.3.8 --- Simulated Annealing --- p.58 / Chapter 5.3.9 --- Soft Module Adjustment --- p.60 / Chapter 5.4 --- Experimental Results --- p.60 / Chapter 5.5 --- Summary --- p.65 / Chapter 6 --- Conclusion --- p.67 / Chapter A --- Appendix --- p.69 / Chapter A.1 --- Well-Known Algorithms --- p.69 / Chapter A.1.1 --- Kruskal's Algorithm --- p.69 / Chapter A.1.2 --- Bellman-Ford Algorithm --- p.69 / Chapter A.2 --- Figures of Resulting Floorplans --- p.71 / Chapter A.2.1 --- Data Set One --- p.71 / Chapter A.2.2 --- Data Set Two --- p.80 / Chapter A.2.3 --- Data Set Three --- p.85 / Chapter A.2.4 --- Data Set Four --- p.92 / Bibliography --- p.98

Com a aprovação da Política Nacional de Resíduos Sólidos, a política de sustentabilidade tende ao reaproveitamento de resíduos, em seu ciclo ou destinação final ambientalmente adequada. Neste contexto, são apresentados neste trabalho, estudos do processo de separação de materiais metálicos e não metálicos encontrados em placas de circuito impresso de microcomputadores e a caracterização dos elementos químicos presentes. Para isto efetuou-se a trituração primária (moagem) das placas de circuito impresso, classificação granulométrica, separação de elementos metálicos e não metálicos utilizando separadores, magnético e eletrostático, separação gravimétrica com o uso de clorofórmio e bromofórmio. Para caracterização dos elementos metálicos e não metálicos, foram utilizadas as técnicas de Espectrometria de fluorescência de Raios X e Espectrometria de infravermelho. Os separadores eletrostático e eletromagnético não foram efetivos na separação de placas de circuito impresso para granulometrias inferiores a 9 Mesh. A separação dos elementos metálicos e não metálicos das amostras com granulometrias inferiores a 9 Mesh, teve eficiência parcial utilizando o clorofórmio, mas mostrou-se efetiva com a utilização do bromofórmio. Embora a separação gravimétrica, não tenha sido efetiva, as amostras foram caracterizadas. Para obter uma melhor separação dos elementos presentes na amostra de não metálicos, procedeu-se a trituração secundária (moagem) desta amostra, resultando na desagregação e separação efetiva. / With the approval of the National Solid Waste Policy, the sustainability policy tends to refer to the reuse of waste materials in its cycle or final destination, environmentally right. In this context, it is introduced in this work a study of metallic and nonmetallic materials separation, found in printed circuit boards of microcomputers and present chemical elements characterization. For this purpose it was performed the primary crushing (grinding) of printed circuit boards, particle size classification, separation of metallic and non-metallic elements by using magnetic and electrostatic separators, gravimetric separation using chloroform and bromoform. For characterization of metallic and nonmetallic elements, were used Spectrometry X-ray fluorescence and infrared spectrometry techniques. The electrostatic and electromagnetic separators were not effective in the separation of printed circuit boards for grain sizes below 9 Mesh. The separation of metallic and non-metallic elements of the samples with particle sizes less than 9 Mesh, had partial efficiency using chloroform, but was effective with the use of bromoform. Although the gravimetric separation, has not been effective, the characterized samples were. In order to get better separation of the elements present in non metallic samples it was made the secondary crushing (grinding) of this sample resulting in the breakdown and effective separation.

One central question of neuroscience asks how a neural system can generate the diversity of complex behaviors needed to meet the range of possible demands placed on an organism by an ever changing environment. In many cases, it appears that animals assemble complex behaviors by recombining sets of simpler behaviors known as behavioral primitives. The crawling behavior of the nematode worm Caenorhabditis elegans represents a classic example of such an approach since worms use the simple behaviors of forward and reverse locomotion to assemble more complex behaviors such as search and escape. The relative simplicity and well-described anatomy of the worm nervous system combined with a high degree of genetic tractability make C. elegans an attractive organism with which to study the neural circuits responsible for assembling behavioral primitives into complex behaviors. Unfortunately, difficulty probing the physiological properties of central synapses in C. elegans has left this opportunity largely unfulfilled. In this dissertation we address this challenge by developing techniques that combine whole-cell patch clamp recordings with optical stimulation of neurons. We do this using transgenic worms that express the light-sensitive ion channel Channelrhodopsin-2 (ChR2) in putative pre-synaptic neurons and fluorescent protein reporters in the post-synaptic neurons to be targeted by electrodes. We first apply this new approach to probe C. elegans circuitry in chapter II where we test for connectivity between nociceptive neurons known as ASH required for sensing aversive stimuli, and premotor neurons required for generating backward locomotion, known as AVA. In chapter III we extend our analysis of the C. elegans locomotory circuit to the premotor neurons required for generating forward locomotion, known as AVB. We identify inhibitory synaptic connectivity between ASH and AVB and between the two types of premotor neurons, AVA and AVB. Finally, we use our observations to develop a biophysical model of the locomotory circuit in which switching emerges from the attractor dynamics of the network. Primitive selection in C. elegans may thus represent an accessible system to test kinetic theories of decision making. This dissertation includes previously published co-authored material.

The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.