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Conventional wire bond power modules have limited application for high-current operation, mainly because of their poor thermal management capability. Planar power modules have excellent thermal management capability and lower parasitic inductance, which means that the planar packaging method is desirable for high-power applications. For these reasons, a planar power module for an automotive motor drive system was developed, and a gate-driver circuit with an over-current protection was planned to integrate into the module. This thesis discusses a current-sensing method for the planar module, and the integrated gate driver circuit with an over-current protection. After reviewing several current-sensing methods, it becomes clear that most popular current-sensing methods, such as the Hall-Effect sensor, the current transformer, the Shunt resistor, and Rogowski coils, exhibit limitations for the planar module integration. For these reasons, a giant magneto resistive (GMR) magnetic-field detector was chosen as a current-sensing method. The GMR sensor utilizes the characteristics of the giant magneto resistive (GMR) effect in that it changes its resistance when it is exposed to the magnetic-flux. Because the GMR resistor can be fabricated at the wafer level, a packaged GMR sensor is very compact when compared with conventional current sensors. In addition, the sensor detects magnetic-fields, which does not require direct contact to the current-carrying conductor, and the bandwidth of the sensor can be up to 1 MHz, which is wide enough for the switching frequencies of most of motor drive applications. However, there are some limiting factors that need to be considered for accurate current measurement: • Operating temperature • Magnetic-flux density seen by a GMR resistor • Measurement noise If the GMR sensor is integrated into the power module, the ambient temperature of the sensor will be highly influenced by the junction temperature of the power devices. Having a consistent measurement for varying temperature is important for module-integrated current sensors. An experiment was performed to see the temperature characteristics of a GMR sensor. The measurement error caused by temperature variation was quantified by measurement conditions. This thesis also proposes an active temperature error compensation method for the best use of the GMR sensor. The wide current trace of the planar power module helps to reduce the electrical/thermal resistance, but it hinders having a strong and constant magnetic-field-density seen by the GMR sensor. In addition, the eddy-current effect will change the distribution of the current density and the magnetic-flux-density. These changes directly influence the accurate measurement of the GMR sensor. Therefore, analyzing the magnetic-flux distribution in the planar power module is critical for integrating the GMR sensor. A GMR sensor is very sensitive to noise, especially when it is sensing current flowing in a wide trace and exposed to external fields, neither of which can be avoided for the operation of power modules. Post-signal processing is required, and the signal-conditioning circuit was designed to attenuate noise. The signal-conditioning circuit was designed using an instrumentation amplifier, and the circuit attenuated most of the noise that hindered accurate measurement. The over-current protection circuit along with the gate driver circuit was designed, and the concept was verified by experiments. The main achievements of this study can be summarized as: • Characterization of conventional current-sensing methods • Temperature characterization of the GMR resistor • Magnetic-flux distribution of the planar power module • Design of the signal-conditioning circuit and over-current protection circuit / Master of Science

Rail à rail entrée - sortie, classe AB, faible consommation sont autant de critères que le concepteur d'amplificateur opérationnel (AOP) intègre pour réaliser une cellule analogique performante. Pour un AOP standard, l'accent n'est pas porté sur une caractéristique particulière mais sur l’ensemble de celle-ci. Dans le but d'augmenter le nombre de fonction par circuit intégré, la tension d'alimentation des AOPs ainsi que leur consommation en courant tendent à diminuer. L'objectif des circuits réalisés est de doubler le facteur de mérite des circuits déjà présents dans le portefeuille de STMicroelectronics. Le facteur de mérite est un indice qui compare des circuits équivalents. Il est défini par le rapport entre le produit capacité de charge x produit gain bande-passante et le produit courant de consommation x tension d'alimentation. L'état de l'art des structures d'AOPs a orienté l'étude vers des structures analogiques possédant au moins trois étages de gain. Un niveau de gain statique supérieur à la centaine de décibel est nécessaire pour utiliser ces amplificateurs dans des systèmes contre-réactionnés. Puisque chaque étage de gain introduit un noeud haute impédance et que chaque noeud haute impédance est à l'origine d'un pôle, l'étude de la compensation fréquentielle s'est avérée indispensable pour obtenir des structures optimisées. Pour simplifier l'étude de ces AOPs, le développement d'outils d'aide à la conception analogique a contribué à l'automatisation de plusieurs tâches.. Ces différents travaux ont été ponctués par la réalisation et la caractérisation de six circuits. Les compensations fréquentielles utilisées dans ces circuits sont la compensation nested miller , la compensation reversed nested miller et la compensation multipath nested miller . Parmi les six circuits, une moitié a été réalisée uniquement dans le but de valider des concepts de compensation fréquentielle et l'autre moitié avec toutes les contraintes d'une documentation technique propre à la famille d'AOP standard. / To be in line with the standard of operational amplifier (opamp), designer integrates in his circuit several functionalities like a Rail to rail input and output, class AB output stage and low power consumption. For standard products, there is no outstanding performance but the average of all of them has to be good. In order to increase the number of functions on an integrated circuit, the power supply and current consumption are permanently decreasing. The aim of the designed circuits is to double the figure of merit (FOM) of the actual ST portfolio products. The FOM allows the comparison of similar opamps. It is defined by the ratio of the product of capacitive load x gain-bandwith product over the power consumption. The opamps’ state of the art has led this study to three stages analog cells. A DC gain higher than hundreds of decibel is required to use opamps in feedback configuration. As each stage of the structure introduces a high impedance node and as each high impedance node introduces a pole, the study of frequency compensation technics became essential for well optimized structures. To simplify the study of the opamps, three tools have been developed to help in the design of the frequency compensation network and to automate some tasks. This work has been followed by the realization of six cells. Three of them were designed to validate frequency compensation structure and the other three to satisfy a standard opamp datasheet. Nested Miller, Reversed Nested Miller and Multipath Nested Miller compensations were used in these circuits.

O objetivo central desta tese é analisar as transformações da economia urbana londrinense, particularmente de seu circuito inferior, à luz das variáveis que caracterizam o período atual, o período da globalização. Para tanto, dividimos a presente tese em duas partes. Na primeira, analisamos as sucessivas modernizações efetivadas em Londrina e as transformações na divisão territorial do trabalho que redundaram em diferentes especializações produtivas a partir da década de 1930. Na segunda parte, analisamos a organização e o funcionamento de três atividades do circuito inferior da economia urbana: o pequeno comércio estabelecido no Camelódromo de Londrina, o serviço de Mototáxi e o serviço de Entregas Urbanas realizado por motoboys. As conclusões a que chegamos revelam que, no período atual, a dinâmica do meio construído é um dado fundamental da economia urbana. Os fluxos que se efetivam a partir das atividades investigadas envolvem a redefinição dos papéis de intermediação que caracterizam Londrina como uma cidade média da Região Concentrada. O circuito inferior atual apresenta diferenças importantes em relação àquele que se formou em Londrina ao longo dos anos 1970, tais como: as trajetórias dos trabalhadores no mercado de trabalho, a importância dos processos migratórios do campo para a cidade, as escalas de ação de cada circuito, suas formas de integração, entre outras. Estas diferenças são conseqüências das modernizações na economia urbana inerentes à expansão e difusão espacial do meio técnico-científico-informacional. / The central objective of this thesis is to analyze the transformation of the urban economy Londrina, particularly to its lower circuit in the light of variables that characterize the current period, the period of globalization. To this end, we have divided this thesis into two parts. At first, we analyze the successive modernization that happened in Londrina and the changes in the territorial division of labor that resulted in different productive specializations from the 1930s. In the second part, we analyze the organization and operation of three activities of lower circuit of the urban economy: the small business set out in Camelódromo of Londrina, the Moto Táxi service and service performed by Urban Delivery couriers. The conclusions reached show that in the current period, the dynamics of the built environment is a fundamental element of the urban economy. The flows that happen based on the investigated activities involve the redefining of intermediation roles that featuring Londrina city as medium town in the Concentrated Region of Brasil The contemporaneous lower circuit shows major differences when it compares with the lower circuit formed in Londrina in the 1970s, like these: the trajectories of workers in the labor market, the importance of migration from the countryside to the city, the scales of action of upper and lower circuits, its forms of integration, among others. These differences are consequences of modernizations in the urban economy. Besides, theyre inherent at expansion and spatial diffusion of technico-scientific-informational milieu.

L'objet de cette thèse est l'étude de deux méthodes de génération automatique de vecteurs de test pour les circuits intégrés digitaux. Après un rappel des problèmes actuels posés par le test des circuits VLSI (partie I), deux méthodes de génération automatique de vecteurs de test adressant deux types différents d'hypothèses de pannes sont présentées: une méthode heuristique de génération de vecteurs (partie II) et une méthode de test pseudo-exhaustif (partie III)

With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.

As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.

ABSTRACT Federal regulations have recognized that arc flash hazards are a critical source of potential injury. As a consequence, in order to work on some electrical equipment, the energy source must be completely shut-down. However, power distribution systems in mission critical facilities such as hospitals and data centers must sometimes remain energized while being maintained. In recent years the Arc Flash Hazard Analysis has emerged as a power system tool that informs the qualified technician of the incident energy at the equipment to be maintained and recommends the proper protective equipment to wear. Due to codes, standards and historically acceptable design methods, the Arc Flash Hazard is often higher and more dangerous than necessary. This dissertation presents detailed methodology and proposes alternative strategies to be implemented at the design stage of 600 volt facility power distribution systems which will decrease the Arc Flash Hazard Exposure when compared to widely used code acceptable design strategies. Software models have been developed for different locations throughout a power system. These software model simulations will analyze the Arc Flash Hazard in a system designed with typical mainstream code acceptable methods. The model will be changed to show implementation of arc flash mitigation techniques at the system design level. The computer simulations after the mitigation techniques will show significant lowering of the Arc Flash Hazard Exposure.