Langages de description et de spécification du matériel. Le système et le langage CADOC-LD. Modélisation et simulation de dispositifs de bas niveau, technologie MOS

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A novel method for modeling bends in coplanar waveguides (CPWs) is described. The CPW can be viewed as a pair of parallel coupled quasi-slot lines. Bends in the CPW are modeled as a non-uniform coupled line system in terms of their even- and odd- mode characteristics. This modeling approach is general and can be applied for bends with different angles and other similar discontinuities in the CPW. The salient feature of the model is the simplified illustration of frequency dependent effects in the bend. Right-angle, 45 degree, and mitered right-angle bends in the CPW are analyzed, and models are developed for each bend structure. The procedure for extracting the modal scattering matrix from the model is presented. To demonstrate the accuracy of the model, modal transmission coefficients obtained from the model are compared with full-wave electromagnetic simulations. Good agreement between the model and full-wave simulation results over a wide frequency range is demonstrated. The transfer of energy between even and odd modes in the bend is investigated and the effect of the physical properties of the CPW on mode conversion is analyzed in detail. Mode conversion at discontinuities like the bend in CPWs cause non-ideal behavior in the two-port (even-mode) measurements of such circuits. Theoretical prediction of the measured response is discussed along with the predicted response for transmission coefficient from model and full-wave simulations. Comparison between the measurements of a right-angle bend and the corresponding model results shows good agreement. Implementation of the model in SPICE is also discussed. / Graduation date: 2004

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In this thesis, we studied the narrowband power line communication system. This system mainly utilizes the 60Hz power line as the medium to transmit network signals. In the beginning, we studied the power line channel characteristics and the coupling circuit structure, that was used to couple the signal to the power line. Impedance mismatch and signal attenuation may occur when the loading in the power line network changes. To this end we added a driver to the coupling circuit to reduce the output impedance, and hence enhance signal magnitude. In addition, we add the cross-phase coupling circuit with bandpass filter characteristics at the 220V socket. It was found that our cross-phase coupling circuit was able to improve the performance of the power line communication system when cross-phase transmission took place. Finally, we simulated the indoor power line network environment, measured several kinds of residential appliance noise and analyzed the influence on the power line communication system of the appliance noise.

In this study, we add an additional layer above and under the CIGS absorber layer as a secondary absorption layer respectively. We made the conventional structure of ZnO/CdS/CIGS/Mo becomes the structure of ZnO/CdS/CIGS/InGaP/Mo and ZnO/CdS/InGaP/CIGS/Mo which can improve the conversion efficiency. And we translate the thickness proportion of Ga and the doping concentration to find out the best parameter. According to the simulation, the wavelength of EQE in 600 nm ~ 1200 nm for our proposed CIGS solar cell which the additional layer under CIGS layer has been improved when compared to the conventional CIGS solar cell. The short-circuit current density has been increased about 9 %. And the conversion efficiency has also been increased about 9 %.When the additional layer above the CIGS absorber layer, according to the simulation, the wavelength of EQE in 300 nm ~ 600 nm for our proposed CIGS solar cell is improved when compared with the conventional CIGS solar cell. The short-circuit current density has been improved about 7.7 %, the open-circuit voltage about 7.1 %, and the conversion efficiency about 20.6 %. The main reason is that when the InGaP absorption layer under the CIGS layer which can catch the light which can¡¦t be absorbed by CIGS layer. The InGaP absorption layer above the CIGS layer which can catch the light immediately.

In this thesis, a switched-current sigma-delta modulator (SDM) with op-amp active integrator is proposed. The major study is focused on using the op-amp to reduce the input impedance for high speed and high solution and utilizes the dummy switch to decrease the clock feedthrough (CFT) error. We use a sample-and-hold circuit which consists of an op-amp active memory cell and a dummy switch circuit to implement the integrator. It is applied to the building blocks of SDM. The modulator is a second order sigma-delta modulator. A current comparator transforms the current signal into digital voltage signal. A single-bit digital-to-analog (D/A) feedback circuit is used to convert the one-bit digital output to the SI integrator .The modulator is designed in the current mode technique. The delta-sigma modulator simulates using the parameters of the TSMC 0.35£gm CMOS process. The simulation results show that the signal to noise plus distortion ratio (SNDR) is 72 dB, the sampling rate is 10.24MHz, the oversampling ratio is 128, the power consumption is 21mW, the dynamic range is about 70dB, and the power supply is 3.3V. Furthermore, the circuit is verified by cadence-hspice simulation.

We study the relationship between size and depth for Boolean circuits. Over four decades, very few results were obtained for either special or general Boolean circuits. Spira showed in 1971 that any Boolean formula of size s can be simulated in depth O(log s). Spira's result means that an arbitrary Boolean expression can be replaced by an equivalent "balanced" expression, that can be evaluated very efficiently in parallel. For general Boolean circuits, the strongest known result is that Boolean circuits of size s can be simulated in depth O(s / log s). We obtain significant improvements over the general bounds for the size versus depth problem for special classes of Boolean circuits. We show that every layered Boolean circuit of size s can be simulated by a layered Boolean circuit of depth O(sqrt{s log s}). For planar circuits and synchronous circuits of size s, we obtain simulations of depth O(sqrt{s}). Improving any of the above results by polylog factors would immediately improve the bounds for general circuits. We generalize Spira's theorem and show that any Boolean circuit of size s with segregators of size f(s) can be simulated in depth O(f(s)log s). This improves and generalizes a simulation of polynomial-size Boolean circuits of constant treewidth k in depth O(k² log n) by Jansen and Sarma. Since the existence of small balanced separators in a directed acyclic graph implies that the graph also has small segregators, our results also apply to circuits with small separators. Our results imply that the class of languages computed by non-uniform families of polynomial size circuits that have constant size segregators equals non-uniform NC¹. As an application of our simulation of circuits in small depth, we show that the Boolean Circuit Value problem for circuits with constant size segregators (or separators) is in deterministic SPACE (log² n). Our results also imply that the Planar Circuit Value problem, which is known to be P-Complete, is in SPACE (sqrt{n} log n). We also show that the Layered Circuit Value and Synchronous Circuit Value problems, which are both P-complete, are in SPACE(sqrt{n}). Our study of circuits with small separators and segregators led us to obtain space efficient algorithms for computing balanced graph separators. We extend this approach to obtain space efficient approximation algorithms for the search and optimization versions of the SUBSET SUM problem, which is one of the most studied NP-complete problems. Finally we study the relationship between simultaneous time and space bounds on Turing machines and Boolean circuit depth. We observe a new connection between planar circuit size and simultaneous time and space products of input-oblivious Turing machines. We use this to prove quadratic lower bounds on the product of time and space for several explicit functions for input-oblivious Turing machines. / text

In this work a low voltage and highly linear current-mode current to delay (CTD) converter is presented. The proposed current to delay converter has the improved linearity of about 23.5% when compared with a conventional–delay inverter over the input dynamic current range of 50µA. When used as front-end block in current-mode delay-mode analog to digital converter an 11-bit resolution is obtained. The design is implemented in TSMC 90 nm CMOS technology. Monte Carlo analysis and process corner analysis is performed on the proposed circuit to analyze the amount of mismatch that will degrade the performance of the circuit in a system level. A Process, Voltage, and Temperature (PVT) variation insensitive circuit is used to bias the designed CTD converter to obtain 57% reduction of variation when compared with the simple current mode biasing technique.

Thesis (Ed.D.)--Teachers College, Columbia University, 1962. / Typescript; issued also on microfilm. Includes tables. Sponsor: Norton L. Beach. Dissertation Committee: Phil C. Lange. Includes bibliographical references (leaf 158).