In developing a compact electro-optic sampling system for industrial use it is desirable to utilize a semiconductor laser diode as the light source since these devices are compact and economical. This thesis investigates several novel laser driver techniques for generating extremely short optical gain switched pulses from a semiconductor laser diode. These techniques include a novel bias control scheme in which the bias to a semiconductor laser diode, that is being driven with a step recovery diode pulse generator circuit, is turned on and off in order to switch the gain switched optical pulses on and off as desired. The second technique involves a mono-cycle scheme that allows a step recovery diode pulse generator circuit, which is customarily driven by a fixed frequency oscillator, to be driven by a mono-cycle pulse train of variable repetition rate. An equivalent circuit model of a laser diode based on the mono-mode rate equations is discussed and implemented in SPICE for the purpose of studying the interaction of the laser driver circuit electronics and the laser diode. The laser diode equivalent circuit is benchmarked against analytical solutions of the rate equations. A qualitative agreement between the measurements of the laser diode optical and terminal voltage responses and the SPICE simulations of the laser diode equivalent circuit model are demonstrated. / Thesis / Master of Engineering (ME)

This research developed a novel, non-wire bond semiconductor interconnect technology, termed the Dimple Array interconnect (DAI), with significantly improved electrical, thermal and mechanical characteristics for power electronics applications. In the DAI structure, electrical connections onto the devices are achieved by solder bumps formed between the silicon device and arrays of dimples stamped on a metal sheet flex. This research first presents the design of the materials, electrical and thermal performance, reliability, and the fabrication process of the DAI. It was found that due to the use of solder material, the current handling capability and thermal management of Dimple Array interconnected devices are significantly better than those using wire bonds. In addition, the shorter and wider solder joints reduce parasitics, which is a serious problem in wire bond interconnects. The proposed fabrication process of the DAI is simpler than other developing integrated power packaging technologies, such as flip chip and deposited metallization integration. DAI was successfully demonstrated in a half-bridge power electronics module with much improved electrical characteristics. The study then focuses on the thermomechanical reliability of Dimple Array packages as compared to conventional controlled collapse bonding (CCB) flip chip packages. Experimental approaches, such as power cycling and temperature cycling tests, and numerical simulation with the help of finite element analysis (FEA) were used. The thermal cycling test shows that dimple solder joints display an eightfold reliability improvement over the conventional CCB solder joints. The power cycling test showed that the measured forward voltage can not reliably reflect the integrity of the solder joint interconnect. However, from metallographic cross-section images of these samples, it was concluded that the DAI solder joints are more reliable than the CCB solder joints under power cycling conditions. FEA results showed excellent correlation with experiments in predicting that the Dimple Array solder joints are more fatigue-resistant due to a reduced stress/strain concentration. Furthermore, failure mechanisms were explored using the mapped stress/strain distribution within the models. It was found that the CCB solder joint has a highly localized strain concentration at the device/solder interface, while strains are more uniformly distributed over the whole Dimple Array solder joint. / Ph. D.

The characterization and modeling of piezoelectric transformers are studied and developed for use in electronic ballasts. By replacing conventional L-C resonant tanks with piezoelectric transformers, inductor-less piezoelectric transformer electronic ballasts have been developed for use in fluorescent lamps. The piezoelectric transformer is a combination of piezoelectric actuators as the primary side and piezoelectric transducers as the secondary side, both of which work in longitudinal or transverse vibration mode. These actuators and transducers are both made of piezoelectric elements, which are composed of electrode plates and piezoelectric ceramic materials. Instead of the magnetic field coupling between the primary and secondary windings in a conventional magnetic core transformer, piezoelectric transformers transfer electrical energy via electro-mechanical coupling that occurs between the primary and secondary piezoelectric elements for isolation and step-up or step-down voltage conversion. Currently, there are three major types of piezoelectric transformers: Rosen, thickness vibration mode, and radial vibration mode, all three of which are used in DC/DC converters or in electronic ballasts for fluorescent lamps. Unlike the other two transformers, the characterization and modeling of the radial vibration mode piezoelectric transformer have not been studied and developed prior to this research work. Based on the piezoelectric and wave equations, the physics-based equivalent circuit model of radial vibration mode piezoelectric transformers is derived and verified through characterization work. Besides the major vibration mode, piezoelectric transformers have many spurious vibration modes in other frequency ranges. An improved multi-branch equivalent circuit is proposed, which more precisely characterizes radial vibration mode piezoelectric transformers to include other spurious vibration modes in wide frequency ranges, as compared with the characterizations achieved by prior circuits. Since the equivalent circuit of piezoelectric transformers is identical to the conventional L-C resonant tank used in electronic ballasts for fluorescent lamps, piezoelectric transformers replace the conventional L-C resonant tank in order to reduce the amount and cost of electronic components for the electronic ballasts. With the inclusion of the radial vibration mode piezoelectric transformer, the design and implementation of inductor-less piezoelectric transformer electronic ballast applications have been completed. / Ph. D.

Neutral gas pressure measurements in low Earth orbit (LEO) can facilitate the monitoring of atmospheric gravity waves, which can trigger instabilities that severely disrupt radio frequency communication signals. The Space Neutral Pressure Instrument (SNeuPI) is a low-power instrument detecting neutral gas density in order to determine neutral gas pressure. SNeuPI consists of an ionization chamber and a logarithmic electrometer circuit. The Rev. 1 SNeuPI electrometer prototype does not function as designed. A Rev. 2 electrometer circuit must be designed and its performance characterized across specified operating temperature and input current ranges. This document presents a design topology for the Rev. 2 electrometer and a derivation of the theoretical circuit transfer function. Component selection and layout are discussed. A range of predicted operating input currents is calculated using modeled neutral density data for a range of local times, altitudes, and latitudes corresponding to the conditions expected for the Lower Atmosphere/Ionosphere Coupling Experiment (LAICE) CubeSat mission. Laboratory test setups for measurements performed both under vacuum and at atmospheric pressure are documented in detail. Test procedures are presented to characterize the performance of the Rev. 2 electrometer at a range of controlled operating temperatures. The results of these tests are then extrapolated in order to predict the operation of the circuit at specified temperatures outside of the range controllable under laboratory test conditions. The logarithmic conformance, accuracy, sensitivity, power consumption, and deviations from expected response of the circuit are characterized. The results validate the electrometer for use under its expected flight conditions. / Master of Science

The objective of this research project was to develop and implement a model for an A.C circuit breaker in the Electromagnetic Transients Program (EMTP). Various models for the arcing process were evaluated, and the modified Mayr equation was chosen for the model. Other equations were added to demonstrate the generality of the algorithm developed. Since the Electromagnetic Transients Program was not designed to accommodate directly elements whose resistance varies with time, such as an electric arc, several strategies for interfacing the model with the program were studied. The compensation method was selected, and was used for interfacing the circuit breaker model with the program. After implementation of the model, it was validated by comparing its performance with experimentally verified results reported previously. In order to render the model more practical, an auxiliary breaker parameter estimation routine was developed and tested. / M.S.

The dramatic increase in market demand for wireless products has inspired a trend for new designs. These designs are smaller, less expensive, and consume less power. A natural result of this trend has been the push for components that are more highly integrated and take up less real estate on the printed circuit board (PCB). Major efforts are underway to reduce the number of integrated circuits (ICs) in newer designs by incorporating several functions into a single chip. Availability of newer technologies such as silicon bipolar with complementary metal oxide semiconductor (BiCMOS) has helped facilitate this move toward more complex circuit topologies onto one die. BiCMOS achieves efficient chip area utilization by combining bipolar transistors, suited for higher frequency analog circuits with CMOS transistors that are useful for digital functions and lower frequency analog circuits. A voltage controlled oscillator (VCO) is just one radio frequency (RF) circuit block that can benefit from a more complex semiconductor process like BiCMOS. This thesis presents the design and evaluation of an integrated VCO in the IBM 5S BiCMOS process. IBM 5S is a 0.5 um, single poly, five-metal process with surface channel PFETs and NFETs. The process also features self-aligned extrinsic base NPN bipolar devices exhibiting ft of up to 24 GHz. The objective of this work is to obtain a VCO design that provides a high degree of functionality while maximizing performance over environmental conditions. It is shown that an external feedback and resonator network as well as a bandgap voltage referenced bias circuit help to achieve these goals. An additional objective for this work is to highlight several pragmatic issues associated with designing an integrated VCO capable of high volume production. The Clapp variant of the Colpitts topology is selected for this application for reasons of robust operation, frequency stability, and ease of implementing in integrated form. Design is performed at 560 MHz using the negative resistance concept. Simulation results from Pspice and the Agilent ADS are presented. Implementation related issues such as bondwire inductances and layout details are covered. The VCO characterization is shown over several environmental conditions. The final nominal design is capable of: tuning over 150 MHz (22%) and delivering â 4.2 dBm into a 50 Ohm load while consuming only 9mA from a 3.0V supply. The phase noise at these conditions is -92.5 dBc/Hz at a frequency offset of 10 kHz from the carrier. Finally, the conclusion of this work lists some suggestions for potential future research. / Master of Science

Thesis (PhD)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: In order to facilitate the creation of complex and robust RSFQ digital logic circuits an extensive library of electronic design automation (EDA) tools is a necessity. It is the aim of this work to introduce various methods to improve the current state of EDA in RSFQ circuit design. Firstly, Monte Carlo methods such as Latin Hypercube sampling and Sobol sequences are applied for their variance reduction abilities in approximating circuit yield. In addition, artificial neural networks are also investigated for their applicability in modeling the parameter-yield space. Secondly, a novel technique for circuit functional testing using automated state machine extraction is presented, which greatly simplifies the logical verification of a circuit. This method is also used, along with critical timing extraction, to automatically generate Hardware Description Language(HDL) models which can be used for high level circuit design. Lastly, the Greedy Local search, Simulated Annealing and Genetic Algorithm meta-heuristics were statistically compared in a novel manner using a yield model provided by artificial neural networks. This is done to ascertain their performance in optimising RSFQ circuits in relation to yield. The variance reduction techniques of Latin Hypercube Sampling and Sobol sequences were shown to be beneficial for the use with RSFQ circuits. For optimisation purposes the use of Simulated Annealing and Genetic Algorithms were shown to improve circuit optimisation for possible multi-modal search spaces. An HDL model is also successfully generated from a complex RSFQ circuit for use in high level circuit design which includes critical timing and propagation latency. All the techniques presented in this study form part of a software library that can be further refined and extended in future work.

In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variation. A strategy to derive the optimal buffer size and the optimal tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variations. Using HSPICE simulations based on the high performance 32nm ASU Predictive Model, we show that up to 30% average power reduction can be achieved for a SRAM word-line decoder while maintaining the same timing yield. / text

<p>This thesis investigates simulation of synchronous machines using a novel Magnetic Equivalent Circuit (MEC) model. The proposed model offers sufficient detail richness for design calculations, while still keeping the simulation time acceptably short.</p><p>Different modeling methods and circuit alternatives are considered. The selected approach is a combination of several previous methods added with some new features. A detailed description of the new model is given. The flux derivative is chosen as the magnetic flow variable which enables a description with standard circuit elements. The model is implemented in dq-coordinates to reduce complexity and simulation time. A new method to reflect winding harmonics is introduced.</p><p>Extensive measurements have been made to estimate the traditional dq-model parameters. These in combination with analytical calculations are used to determine the parameters for the new MEC model.</p><p>The model is implemented using the Dymola simulation program. The results are evaluated by comparison with measurements and FEM simulations. Three different operation cases are investigated; synchronous operation, asynchronous start and inverter fed operation. The agreement with measurements and FEM simulations varies, but it is believed that it can be improved by more work on the parameter determination.</p><p>The overall conclusion is that the MEC method is a useful approach for detailed simulation of synchronous machines. It enables proper modeling of magnetic saturation, and promises sufficiently detailed results to enable accurate loss calculations. However, the experience is that the complexity of the circuits should be kept at a reasonable low level. It is believed that the practical problems with model structure, parameter determination and the simulation itself will otherwise be difficult to master.</p>

This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the incorporation of externally measured or calculated scattering parameter data and large system analysis through macro decomposition. The inclusion of non-linear terminations has also been developed.