The boom of mobile communications leads to an increasing request of low cost and low power mixed mode integrated circuits. Maturity of SOI technology, and recent progresses of MOSFET's microwave performances, explain the success of silicon as compared to III-V technologies for low-cost multigigahertz analog applications. The design of efficient circuits requires accurate, wide-band models for both active and passive elements. Within this frame, passive components fabricated in SOI technologies have been studied, and a physical model of integrated square spiral inductors has been developed. Also, the performances of integrated MOSFETs have been analyzed. New alternative structures of transistor (the Graded Channel MOSFET and the Dynamic Threshold MOSFET) have been proposed and studied from Low to High frequencies. These transistors show very interesting properties for analog, low power, low voltage, and microwave applications. Furthermore, as their fabrication processes are fully CMOS compatible, they allow us to increase the performances of a CMOS technology without any modification of its process, and without extra-cost.

With the increasing system clock, a clock circuit will cause an amount of electromagnetic interference. To reduce EMI of the products, various EMI strategies have been developed. In the thesis, we study the suppression of electromagnetic interference of a clock circuit by using the spread spectrum technique. The basic idea of the spread spectrum is to slightly modulate the frequency of the clock signal and the energy of the signal will be dispersed to a controllable range to reduce the peak energy of each harmonic wave in the spectrum, and the products can pass the electromagnetic compatibility test more easily. We obtain the attenuation factor of spread spectrum from the theoretical derivation, including modulation index and modulation profiles. From the numerical simulation, we verify that spread spectrum technique can suppress the peak energy. We propose the attenuation formulas which can control the attenuation of every frequency point. To verify our findings, we use a spread spectrum clock generator from market to perform measurement. The trapezoidal waveform can be used to represent a clock circuit. Its waveform includes rise time and duty cycle. We will discuss the influence of rise time and duty cycle on the spread spectrum technique. Shorter rise time will cause high order harmonics in the high speed clock circuit. We verify that spread spectrum technique can suppress high order harmonics from both the simulation and experiment. Because every harmonic can be suppressed, the spread spectrum technique has the good suppression effect for the whole system.

In the System-on-Chip (SoC) era, common industry estimates are that functional verification takes approximately 70% of the total effort on a project. For the time-to-market constrain, it¡¦s a challenge to reduce the SoC verification/debugging time efficiently. In an SoC, a microprocessor is an essential part of it. First, we focus the debugging problem on microprocessors. An in-circuit emulation (ICE) module that can be embedded with a microprocessor core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typical debugging and testing mechanisms, including boundary scan paths, partial scan paths, single stepping, internal resource monitoring and modification, breakpoint detection, and mode switching between debugging and normal modes. The architecture of the ICE module is parameterized and retargetable to different microprocessors. It has been successfully integrated with two microprocessors with significantly different architectures: one 8-bit industrial embedded microcontroller HT48x00 and one 32-bit ARM7-like embedded microprocessor. FPGA prototypes and chip implementation have been accomplished. Experiments show that real-time (on-line) debugging at full speed is possible with the embedded ICE at a minor gate count overhead. Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress program execution traces in real time in order to reduce the trace size. The approach consists of three modularized phases: (1) branch/target filtering, (2) branch/target address encoding and (3) Lempel-Ziv-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1K to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1). For SoC debugging, bus signal tracing represents that the information which is generated from the system can be collected for later observation, debugging and analysis. However, the generation rate and the size of real time system traces are so huge such that a mechanism for system tracing that can reduce trace size efficiently is needed. In this paper, we propose a multi-resolution bus trace approach. The hardware bus tracer consists of two major stages: (1) signal monitor & tracing stage, and (2) trace compression stage. In the first stage, designer can trace the signals in detail or in rough depends on the debug purpose. In other word, the multi-resolution trace approach provides the trade-off between trace accuracy and trace depth. In the second stage, the bus tracer compresses the trace size efficiently; therefore the capability of on-chip storage is increased. In the host, the analyzer tool decompresses the trace data for future observation and debugging.

This thesis presents the VLSI implementation and characterization of a 256-channel bidirectional integrated neural interface for adaptive cortical stimulation. The microsystem consists of 64 stimulation and 256 recording channels, implemented in a 0.35um CMOS technology with a cell pitch of 200um and total die size of 3.5mm x3.65mm. The stimulator is a current driver with an output current range of 20uA – 250uA. The current memory in every stimulator allows for simultaneous stimulation on multiple active channels. Circuit reuse in the stimulator and utilization of a single DAC yields a compact and low-power implementation. The recording channel has two stages of signal amplification and conditioning and a single-slope ADC. The measured input-referred noise is 7.99uVrms over a 5kHz bandwidth. The total power consumption is 13.3mW. A new approach to CMOS-microelectrode hybrid integration by on-chip Au multi-stud-bumping is also presented. It is validated by in vitro experimental measurements.

This thesis presents the VLSI implementation and characterization of a 256-channel bidirectional integrated neural interface for adaptive cortical stimulation. The microsystem consists of 64 stimulation and 256 recording channels, implemented in a 0.35um CMOS technology with a cell pitch of 200um and total die size of 3.5mm x3.65mm. The stimulator is a current driver with an output current range of 20uA – 250uA. The current memory in every stimulator allows for simultaneous stimulation on multiple active channels. Circuit reuse in the stimulator and utilization of a single DAC yields a compact and low-power implementation. The recording channel has two stages of signal amplification and conditioning and a single-slope ADC. The measured input-referred noise is 7.99uVrms over a 5kHz bandwidth. The total power consumption is 13.3mW. A new approach to CMOS-microelectrode hybrid integration by on-chip Au multi-stud-bumping is also presented. It is validated by in vitro experimental measurements.

Few studies have examined the acute effects of resistive-type exercise on lipid-lipoprotein profiles. This study examined the acute effects of a single session of circuit weight training (CWT) on plasma lipid-lipoprotein profiles: triglycerides (TG), total cholesterol (TC), high density lipoprotein cholesterol (HDL-C), low density lipoprotein cholesterol (LDL-C), and the ratio of TC to HDL-C. The subjects in the study were 17 healthy, nonsmoking male university students, ages of 18-25 years, enrolled in weight lifting classes. Subjects were required to fast overnight (at least 12 hours) before CWT. Subjects repeated a four-station weight training circuit three times, with a resistance determined by their individual 3 repetition maximum (3-RM). The stations were bench press, parallel squat, leg extension, and seated row. Blood samples were drawn from the antecubital vein at pre-CWT, completion of the 1st and 3rd circuits, and 15 min post-CWT. All concentrations of plasma lipid and lipoprotein cholesterol were corrected for plasma volume changes. A repeated measures ANOVA was used to determine if significant differences existed among mean values for the dependent variables (i.e., levels of TG, TC, HDL-C, LDL-C, and TC/HDL-C ratio at specified time points). Results of the study indicated that plasma TC and HDL-C levels were changed significantly during and following CWT. However, the change was not in the anticipated direction: Plasma TC and HDL-C levels were lower at completion of the 1st circuit of CWT (p<0.05). The ratios of TC to HDL-C were changed significantly, reflecting a decrease in HDL-C during CWT and a slight increase in HDL-C at 15 min post-CWT. Plasma TG and LDL-C levels were not changed significantly during CWT or 15 min post-CWT. It was concluded that apparent changes in lipoprotein patterns occur during short-term moderate intensity CWT and return to pre-CWT levels in a relatively short time. / Graduation date: 1991

The continued scaling of digital integrated circuits has led to an increasingly larger impact of process, supply voltage, and temperature (PVT) variations. The effect of these variations on logic cell and interconnect delays has introduced challenges to both circuit performance (timing)verification and optimization. In order for us to fully take advantage of the benefits of technology scaling, it is essential that ``variation-aware''techniques for performance verification and optimization be developed and used in modern design flows. In this thesis such techniques for both performance verification and optimization are presented. First, we present a fast method for finding the worst-case slacks over all process and environmental corners. This method uses the standard set of PVT corners available in industry, and provides large runtime gains while maintaining a high degree of accuracy. After that, we propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delays at every point in the parameter space, by reporting all paths that can become critical. This method employs parameterized static timing analysis (PSTA) variability models, and allows one to easily examine local robustness to parameters in different regions of the parameter space. Next, we introduce an optimization method that alters clock network lines so that a circuit meets its timing constraints at all PVT settings under PSTA variability models. This is formulated as a Linear Program (LP), which is based on a clock skew optimization formulation, and as a result it can be solved efficiently. Finally, we present a method that uses characterized, pre-silicon, PSTA variational timing models to identify speedpaths that can best explain the observed delay measurements during silicon debug. This is a crucial step, required for both ``fixing'' failing paths and for accurate learning from silicon data.

In this research a unique linear pulse amplifier was developed that significantly reduces the spread in pulse amplitudes of those pulses selected from a Ge(Li) detector by a single channel analyzer. This circuit utilizes an operational amplifier with its closed-loop gain automatically controlled by a P-channel junction field.-effect transistor. The amplification is adjusted for each pulse such that the output pulses are constant in amplitude. The performance of the system was analyzed with a multichannel analyzer and it was shown that an improvement in pulse amplitude variation of as much as 29.1 percent was achieved.Ball State UniversityMuncie, IN 47306

The continued scaling of digital integrated circuits has led to an increasingly larger impact of process, supply voltage, and temperature (PVT) variations. The effect of these variations on logic cell and interconnect delays has introduced challenges to both circuit performance (timing)verification and optimization. In order for us to fully take advantage of the benefits of technology scaling, it is essential that ``variation-aware''techniques for performance verification and optimization be developed and used in modern design flows. In this thesis such techniques for both performance verification and optimization are presented. First, we present a fast method for finding the worst-case slacks over all process and environmental corners. This method uses the standard set of PVT corners available in industry, and provides large runtime gains while maintaining a high degree of accuracy. After that, we propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delays at every point in the parameter space, by reporting all paths that can become critical. This method employs parameterized static timing analysis (PSTA) variability models, and allows one to easily examine local robustness to parameters in different regions of the parameter space. Next, we introduce an optimization method that alters clock network lines so that a circuit meets its timing constraints at all PVT settings under PSTA variability models. This is formulated as a Linear Program (LP), which is based on a clock skew optimization formulation, and as a result it can be solved efficiently. Finally, we present a method that uses characterized, pre-silicon, PSTA variational timing models to identify speedpaths that can best explain the observed delay measurements during silicon debug. This is a crucial step, required for both ``fixing'' failing paths and for accurate learning from silicon data.

FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link.