With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its application. We need to have a more efficient core processor to support the whole embedded system in complex system environment. The main purpose of this paper is increased the calculated speed, memory management and debugging for SYS32TME III, which is designed by our lab as an ARM10 like processor. We integrate the cache/MMU and EICE( Embedded in-circuit emulator ) into the embedded processor core. Using the cache/MMU, we can not only speed up the processor which access external memory time but also use the virtual address for Operating System. In order to keep the correctness of the system and speed up the system integration time, we use five functional (cache off, cache on and MMU off with cache hit/miss, cache on and MMU on with cach hit/cache miss and TLB hit/cache miss and TLB miss) tests to verify the cache/MMU and six coprocessor instructions (LDC, MCR, MCRR, MRC, MRRC, STC ) to verify the EICE. After that, we also use the regression test about the microprocessor, cache/MMU and EICE system integration. In the end, we turned the performance about the integrated cache/MMU and EICE, so that we can support an 200MHz ARM 10-like processor by 0.18£gm.

This thesis consists of two topics. A frequency-shift readout circuit is integrated for the rapid IgE measurement biomedical system in the first half. Secondly, we present a ROM-less DDFS (direct digital frequency synthesis) using a non-equal division parabolic polynomial interpolation method, which is used as the frequency generator in the measurement system. The first topic investigates the IgE concentration measurement system and realizes the readout circuit using TSMC 1P6M 0.18 £gm CMOS technology. We integrate the flexural plate wave (FPW) sensor chips and an ASIC comprising control block, digital to analog convertor (DAC), OTA-C oscillators, amplifiers, peak detectors, registers, and a subtractor. By taking advantages of the characteristics that the central frequencies of the loaded FPW sensors will be shifted, sine waves with various frequencies are generated and swept through one pair of FPW sensors. The frequency difference of these sensors is then readout to get concentration by look-up table. The second topic investigates the division method of a quarter sine wave to improve the spurious free dynamic range (SFDR) and realizes a ROM-less DDFS which is used as the frequency generator in the mentioned IgE measurement system. The proposed non-equal division parabolic polynomial interpolation method will generate a complete sine wave by a quarter of a sine digital signal owing to the symmetry. We combine the quasi-linear interpolation and an offset adjustment to derive the quarter sine wave digital signals. The proposed method not only reduces the absolute error between ideal sine wave and generated sine wave, it also improves SFDR.

In this thesis, we propose a new structure of GaP/a-Si:H/BulkSi solar cell in which the additional a-Si:H layer due to the concept of energy bandgap is used to improve the open-circuit voltage. As the a-Si:H doping concentration is increased, the upward bandgap bending is expected to be observed; hence, a high open-circuit voltage is obtained. But in this situation, the upward bandgap bending also hinders the carrier transport, leading a low short-circuit current density. It is worth noting that the proposed solar cell can have a high open-circuit voltage of 0.758 V. In addition, we carefully investigate the characteristics of wide-bandgap gallium phosphide (GaP) material used for silicon-based solar cells. According to the simulated results, the absorption of GaP is better than silicon with a wavelength below 450 nm. Also, the GaP/BulkSi solar cell is shown to have a lower reflectivity value than the conventional PN_BulkSi solar cell. Hence we can prove that the internal quantum efficiency and external quantum efficiency are improved accordingly. As a result, the short-circuit current density is increased about 10 %. In addition, the optimized parameters of a GaP/BulkSi solar cell are as follows: the short-circuit current density is 21.264 mA/cm2, the open-circuit voltage is 0.624 V, the fill factor is 82.4 %, the conversion efficiency is 11.236 %, respectively.

The multi-core systems are usually implemented on homogeneous or heterogeneous cores, in order to design the better NOC (network on chip), it must consider the performance, scalability, simplifies hardware design and arbitration strategy at the on chip network. The routers are designed with circuit-switched network, circuit switching is asynchronous circuits and routers have no queuing (buffering), therefore, it is simple and efficient in implementation. Synchronous circuit is network with a clock source, but the distributing global clock has many problems such as power consumption, increasing the area and Clock skew. Ring topology with multi-transaction bus architecture. It could make multiple packets to access the bus at the same time, so that the multi-transaction bus architecture is better to get more throughputs. When the number of cores increase, the central arbiter circuit is more complexity, this thesis presents an SAP (self-adjusting priority) schedule that can fairly adjust priorities of each component by appropriately exchanging weighting at distributed arbiter. When numerous requests encounter contention on a network, a winner owning the highest priority will exchange its priority with the lowest priority of these requests. This principle guarantees that winners will decreased the opportunity of incurring network at the next time. In opposition, these losers can obtain the higher priority than that of the original. Therefore, the proposed scheme not only offers fair strategy, but also simplifies hardware design.

This research addresses some critical challenges in various problems of VLSI design automation, including sophisticated solution search on DAG topology, simultaneous multi-stage design optimization, optimization on multi-scenario and multi-core designs, and GPU-based parallel computing for runtime acceleration. Discrete optimization for VLSI design automation problems is often quite complex, due to the inconsistency and interference between solutions on reconvergent paths in directed acyclic graph (DAG). This research proposes a systematic solution search guided by a global view of the solution space. The key idea of the proposal is joint relaxation and restriction (JRR), which is similar in spirit to mathematical relaxation techniques, such as Lagrangian relaxation. Here, the relaxation and restriction together provides a global view, and iteratively improves the solution. Traditionally, circuit optimization is carried out in a sequence of separate optimization stages. The problem with sequential optimization is that the best solution in one stage may be worse for another. To overcome this difficulty, we take the approach of performing multiple optimization techniques simultaneously. By searching in the combined solution space of multiple optimization techniques, a broader view of the problem leads to the overall better optimization result. This research takes this approach on two problems, namely, simultaneous technology mapping and cell placement, and simultaneous gate sizing and threshold voltage assignment. Modern processors have multiple working modes, which trade off between power consumption and performance, or to maintain certain performance level in a powerefficient way. As a result, the design of a circuit needs to accommodate different scenarios, such as different supply voltage settings. This research deals with this multi-scenario optimization problem with Lagrangian relaxation technique. Multiple scenarios are taken care of simultaneously through the balance by Lagrangian multipliers. Similarly, multiple objective and constraints are simultaneously dealt with by Lagrangian relaxation. This research proposed a new method to calculate the subgradients of the Lagrangian function, and solve the Lagrangian dual problem more effectively. Multi-core architecture also poses new problems and challenges to design automation. For example, multiple cores on the same chip may have identical design in some part, while differ from each other in the rest. In the case of buffer insertion, the identical part have to be carefully optimized for all the cores with different environmental parameters. This problem has much higher complexity compared to buffer insertion on single cores. This research proposes an algorithm that optimizes the buffering solution for multiple cores simultaneously, based on critical component analysis. Under the intensifying time-to-market pressure, circuit optimization not only needs to find high quality solutions, but also has to come up with the result fast. Recent advance in general purpose graphics processing unit (GPGPU) technology provides massive parallel computing power. This research turns the complex computation task of circuit optimization into many subtasks processed by parallel threads. The proposed task partitioning and scheduling methods take advantage of the GPU computing power, achieve significant speedup without sacrifice on the solution quality.

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step.

As CMOS technologies move to sub-100nm regions, the design and verification for analog/mixed-signal circuits become more and more difficult due to the problems including the decrease of transconductance, severe gate leakage and profound mismatches. The increasing manufacturing-induced process variations and their impacts on circuit performances make the already complex circuit design even more sophisticated in the deeply scaled CMOS technologies. Given these barriers, efforts are needed to ensure the circuits are robust and optimized with consideration of parametric variations. This research presents innovative computer-aided design approaches to address three such problems: (1) large analog/mixed-signal performance modeling under process variations, (2) yield-aware optimization for complex analog/mixedsignal systems and (3) on-chip test scheme development to detect and compensate parametric failures. The first problem focus on the efficient circuit performance evaluation with consideration of process variations which serves as the baseline for robust analog circuit design. We propose statistical performance modeling methods for two popular types of complex analog/mixed-signal circuits including Sigma-Delta ADCs and charge-pump PLLs. A more general performance modeling is achieved by employing a geostatistics motivated performance model (Kriging model), which is accurate and efficient for capturing stand-alone analog circuit block performances. Based on the generated block-level performance models, we can solve the more challenging problem of yield-aware system optimization for large analog/mixed-signal systems. Multi-yield pareto fronts are utilized in the hierarchical optimization framework so that the statistical optimal solutions can be achieved efficiently for the systems. We further look into on-chip design-for-test (DFT) circuits in analog systems and solve the problems of linearity test in ADCs and DFT scheme optimization in charge-pump PLLs. Finally a design example of digital intensive PLL is presented to illustrate the practical applications of the modeling, optimization and testing approaches for large analog/mixed-signal systems.

Charging technology is becoming more and more important since rechargeable batteries are commonly used in many applications than ever before. To facilitate various charging profiles, a battery charger with multi-mode is proposed. The charger is composed of an innovative reflex charging circuit and a controllable half-bridge converter with pulse-width-modulation. This multi-mode charger provides not only four basic functions of constant voltage (CV), constant current (CC), pulsed current (PS) and reflex charging (RX), but also the multi-stage charging with hybrid charging modes. The desired charging profile can easily be accomplished by adjusting the controllable parameters of the charger. In order to simplify the control circuit, a digital signal processor (DSP) with the associated sensors and interface circuits are used as the control kernel. By continuously monitoring the charging current and battery voltage, the charging modes can be adapted to the charging strategy. An experimental charging circuit is built and tested. The experiments in this dissertation are carried out on lead-acid batteries, Experimental results show that the charger is able to execute the charging functions of various tentative charging strategies with hybrid charging modes.

The fault phenomena of fluorescent lamps are investigated by observing the operations in the last period of the life cycle. Accordingly, fault detecting and protection circuits are designed. Before coming to the life-end, the lamps can be started up, but are operated abnormally. A ruddy glow may occur at one end of the cathode filaments and an unstable arc may happen to the lamp. Obviously, the light efficiency becomes relatively low. The arc instability eventually results in a totally damaged fluorescent lamp. It is found that both waveforms of the lamp voltage and the lamp current are asymmetrical and have unequal positive and negative peak values. The asymmetry is more significant for the lamp voltage. In addition, a dc component is present in the lamp voltage. Based on these investigated results, the detection and protection circuits are designed for high-frequency electronic ballasts under dimming operations as well at the rated power. The experiments show that the detection and protection circuits can work effectively.

The objective of this thesis is to report the concept of driving a non-contacting steel plate conveyance system with a DSP-based closed-loop control structure. The lift force of the system is first estimated from the magnetic equivalent circuit (MEC) analysis, and the estimation results have been verified through three-dimensional finite element analysis (3-D FEA). Based on the force calculations and the fuzzy control theory, a closed-loop control structure has been designed. Through accurate signal detections, a real-time lift force control of the conveyance system can be realized. Finally, by feeding AC sources with DC bias to the stator windings of the motor, the lift and propulsive forces can be supplied to the steel plate simultaneously.