The transportation sector continues to be a primary source of greenhouse gas (GHG) emissions, contributing more than any other sector in the United States in 2017. Medium-duty and heavy-duty trucks trail only passenger cars as the largest GHG contributor in this sector [1]. The intense operating requirements of these vehicles create a reliance on the diesel engine that is projected to last for many decades. Therefore, it is vital that the efficiency and environmental sustainability of diesel engines continue to be advanced.<br><br>Cylinder deactivation (CDA) is a promising technology to improve diesel engine fuel efficiency and aftertreatment thermal management for emissions reduction. This work presents original experimental results demonstrating fuel efficiency improvements of CDA implemented on a modern engine at idle operating conditions through testing of various CDA configurations. Idle calibration optimizations result in up to 28% fuel consumption reduction at steady-state unloaded idle operation and 0.7% fuel consumption reduction over HD-FTP drive cycles at equivalent emissions levels. The low-load thermal management performance of CDA is also investigated through creep and extended idle transient cycles, during which CDA is shown to reduce fuel consumption by up to 40% with similar thermal management performance and reduced NOx and soot emissions. <br><br>Variants of CDA implementation are explored through an experimental comparison of deactivation strategies. The effort described here compares charge trapping strategies through examination of in-cylinder pressures following deactivation because: (1) choice of trapping strategy dictates the in-cylinder pressure characteristics of the deactivated cylinders, and (2) deactivated cylinders can affect torque, oil consumption, and emissions upon reactivation. Results discussed here suggest no significant differences between the strategies. As an example, the in-cylinder pressures of both trapping strategies are shown to converge as quickly as 0.8 seconds after deactivation.<br><br>Finally, the NVH effects of CDA are characterized through studies of torsional vibration, linear vibration, and acoustics. CDA causes frequency content at reduced frequencies compared to conventional operation, which has effects on all aspects of NVH. This creates possible constraints on achievable fuel efficiency and thermal management performance by restricting CDA usage. An alternate form of CDA, dynamic cylinder activation (DCA), is explored as a possible option of avoiding undesirable frequency output while maintaining the desired engine performance. <br>

This dissertation is focused on studying transport behavior in vapor chambers at ultra-thin form factors so that their use as heat spreaders can be extended to applications with extreme space constraints. Both the steady-state and transient thermal transport behaviors of vapor chambers are studied. The steady-state section presents an experimental characterization technique, methodologies for the design of the vapor chamber wick structure, and a working fluid selection procedure. The transient section develops a low-cost, 3D, transient semi-analytical transport model, which is used to explore the transient thermal behavior of thin vapor chambers: 1) The key mechanisms governing the transient behavior are identified and experimentally validated; 2) the transient performance of a vapor chamber relative to a copper heat spreader of the same external dimensions is explored and key performance thresholds are identified; and 3) practices are developed for the design of vapor chambers under transient conditions. These analyses have been tailored to ultra-thin vapor chamber geometries, focusing on the application of heat spreading in mobile electronic devices. Compared to the conventional scenarios of use for vapor chambers, this application is uniquely characterized by compact spaces, low and transient heat input, and heat rejection via natural convection.

Inversores de sistemas fotovoltaicos são equipamentos de eletrônica de potência que fornecem energia elétrica em corrente alternada (CA) a partir de uma fonte de energia elétrica em corrente contínua (CC), no caso, os módulos fotovoltaicos. Estes inversores quando em operação aumentam sua temperatura. Este aumento de temperatura é indesejável, porém é inerente ao seu funcionamento. Equipamentos eletrônicos possuem um limite seguro de temperatura de operação, acima do qual podem ocorrer instabilidades de operação, redução da vida útil ou até mesmo falha drástica. O conhecimento da eficiência de conversão elétrica e das perdas responsáveis pelo aquecimento é importante para o adequado dimensionamento de inversores quando aplicados em sistemas fotovoltaicos conectados à rede, assim como para o desenvolvimento do inversor como produto. Para proteção, para aumento da vida útil, para maior confiabilidade, para maior estabilidade e para maior segurança de operação de componentes, inversores possuem rotinas em seus algoritmos de controle com estratégias automatizadas dedicadas ao gerenciamento térmico. Estas rotinas de proteção e gerenciamento térmico, sempre quando acionadas, tendem a reduzir a capacidade de conversão de potência do inversor, seja pelo acionamento de um ventilador auxiliar, seja pelo deslocamento do ponto de operação em máxima potência. Fabricantes de inversores tratam deste assunto pelo termo “temperature derating” (em inglês) Esta tese apresenta um estudo relacionado a influência da temperatura sobre o desempenho de inversores fotovoltaicos conectados à rede. Avalia tipos de estratégias de gerenciamento térmico e proteção de uso corrente em inversores comerciais. Apresenta resultados de ensaios experimentais para determinação de parâmetros térmicos característicos dos inversores. Descreve um modelo preditivo da temperatura de operação em regime transiente. A partir da determinação experimental de parâmetros térmicos, o modelo preditivo de temperatura de operação foi implementado no software de simulação dinâmica para dimensionamento e avaliação de sistemas fotovoltaicos FVCONECT, desenvolvido no LABSOL/UFRGS, estando o mesmo apto para simular a operação e estimar perdas anuais de desempenho energético decorrentes das rotinas de gerenciamento térmico, dos seus efeitos e das limitações impostas durante a operação de inversores fotovoltaicos conectados à rede. Um dos resultados da simulação é a evolução da temperatura do inversor, permitindo avaliar a frequência e amplitude dos ciclos térmicos ao qual o inversor é submetido e, consequentemente, determinar uma estimativa para durabilidade do inversor. / Photovoltaic inverters are electronic power devices that provide electrical energy in alternating current (AC) from a source of electrical energy in direct current (DC) - a photovoltaic generator, in this case. Inverters increase their temperature when in operation. This rise in temperature is not desirable, but inherent to its operation. Any electronic equipment has a safe operating temperature limit. When this limit is surpassed, operating instability, life reduction or even drastic failure may occur. The knowledge of the electrical conversion efficiency and the losses responsible for the heating is important for the proper sizing of grid-tie inverters in photovoltaic systems, as well as for the development of the inverter as a product. In order to increase the useful life of the device and its components, for greater reliability, safety, stability and security of operation, inverters have routines in their algorithms of control with automated strategies dedicated to the thermal management. These protection and thermal management routines, whenever activated, tend to reduce the power conversion capacity of the inverter, either by the activation of an auxiliary fan or by the displacement of the operating point at maximum power. Inverter manufacturers address this issue by the term "temperature derating". This thesis presents a methodology to evaluate the influence of the performance of different strategies to avoid excessive temperature of the inverter components on its performance and durability It is also made an evaluation of different thermal management strategies and protection used in commercial inverters. Results of experimental tests for determination of thermal parameters characteristic of the inverters are presented. A predictive model of transient operating inverter temperature is also described. From the experimental determination of thermal parameters, the predictive model of operating temperature was implemented to the FVCONECT, a dynamic simulation software for sizing and evaluation of photovoltaic systems developed in LABSOL / UFRGS. With this modification, the software was able to simulate the operation and estimate losses of energy due to the thermal management routines, their effects and the limitations imposed during the operation of grid-tie inverters. One of the results of the simulation is the evolution of the inverter temperature, allowing to evaluate the frequency and amplitude of thermal cycles to which the inverter is subjected and, as a consequence, an estimate of durability of the inverter.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-10-24T21:20:23Z No. of bitstreams: 1 ALEXANDRE LAZARETTI ZANATTA.DIS.pdf: 3682553 bytes, checksum: f4e0c608791ce6787d609d8099456e04 (MD5) / Rejected by Sheila Dias (sheila.dias@pucrs.br), reason: Devolvido devido ao trabalho que foi enviado ser de outro aluno. No TEDE est? o nome de um aluno com o t?tulo de um trabalho e no arquivo PDF que veio, est? um outro trabalho de outro aluno. on 2018-10-26T13:20:54Z (GMT) / Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-10-26T15:12:04Z No. of bitstreams: 1 GUILHERME MACHADO DE CASTILHOS.DIS.pdf: 4635819 bytes, checksum: a352dd213c362adb08b9c172c053a214 (MD5) / Approved for entry into archive by Caroline Xavier (caroline.xavier@pucrs.br) on 2018-10-30T16:51:02Z (GMT) No. of bitstreams: 1 GUILHERME MACHADO DE CASTILHOS.DIS.pdf: 4635819 bytes, checksum: a352dd213c362adb08b9c172c053a214 (MD5) / Made available in DSpace on 2018-10-30T16:56:34Z (GMT). No. of bitstreams: 1 GUILHERME MACHADO DE CASTILHOS.DIS.pdf: 4635819 bytes, checksum: a352dd213c362adb08b9c172c053a214 (MD5) Previous issue date: 2017-08-10 / Thermal cycles and high temperatures can have a significant impact on the systems performance, power consumption and reliability, which is a major and increasingly critical design metric in emerging multi-processor embedded systems. Existing thermal management techniques rely on physical sensors to provide them temperature values to regulate the system?s operating temperature and thermal variation at runtime. However, on-chip thermal sensors present limitations (e.g., extra power and area cost), which may restrict their use in large-scale systems. In this context, this Thesis proposes a lightweight software-based runtime temperature model, enabling to capture detailed temperature distribution information of multiprocessor systems with negligible overhead in the execution time. The temperature model is embedded in a distributedmemory MPSoC platform, described at the RTL level. Results show that the average absolute temperature error estimation, compared to the HotSpot tool is smaller than 4% in systems with up to 36 processing elements. Task mapping is the process selected to act in the system, using the temperature information generated by the proposed model. Task mapping is the process of assigning a processing element to execute a given task. The number of cores in many-core systems increases the complexity of the task mapping. The main concerns of task mapping for large systems include (i) scalability; (ii) dynamic workload; and (iii) reliability. It is necessary to distribute the mapping decisions across the system to ensure scalability. The workload of emerging many-core systems may be dynamic, i.e., new applications may start at any moment, leading to different mapping scenarios. Therefore, it is necessary to execute the mapping process at runtime to support dynamic workload. The workload assignment plays a major role in the many-core system reliability. Load imbalance may generate hotspots zones and consequently thermal implications. Recently, task mapping techniques aiming at improving system reliability have been proposed in the literature. However, such approaches rely on centralized mapping decisions, which are not scalable. To address these challenges, the main goal of this Thesis is to propose a hierarchical runtime mapping heuristic, which provides scalability and fair thermal distribution. Thermal distribution inside the system increases the system reliability in long-term, due to the reduction of hotspot regions. The proposed mapping heuristic considers the PE temperature as a cost function. The proposal adopts a hierarchical thermal monitoring scheme, able to estimate at runtime the instantaneous temperature at each processing element. The mapping uses the temperature estimated by the monitoring scheme to guide the mapping decision. Results compare the proposal against a mapping heuristic whose main cost function minimizes the communication energy. Results obtained in large systems, show a decrease in the maximum temperature (best case, 8%) and improvement in the thermal distribution (best case, 50% lower standard deviation of processor temperatures). Such results demonstrate the effectiveness of the proposal. Also, a 45% increase in the lifetime of the system was achieved in the best case, using the proposed mapping. / As altas varia??es t?rmicas e de temperatura de opera??o podem ter um impacto significativo no desempenho do sistema, consumo de energia e na confiabilidade, uma m?trica cada vez mais cr?tica em sistema multiprocessados. As t?cnicas de gerenciamento t?rmico existentes dependem de sensores f?sicos para fornecer os valores de temperatura para regular a temperatura de opera??o e a varia??o t?rmica do sistema em tempo de execu??o. No entanto, os sensores t?rmicos em um chip apresentam limita??es (por exemplo, custo extra de pot?ncia e de ?rea), o que pode restringir seu uso em sistemas com uma grande quantidade de processadores. Neste contexto, esta Tese prop?e um modelo de temperatura baseado em software, realizado em tempo de execu??o, permitindo capturar informa??es detalhadas da distribui??o de temperatura de sistemas multiprocessados com custo m?nimo no desempenho das aplica??es. Para validar a proposta, o modelo foi inclu?do em uma plataforma MPSoC com mem?ria distribu?da, descrita no n?vel RTL. Al?m disso, os resultados mostram que o erro absoluto m?dio da estimativa de temperatura, em compara??o com a ferramenta HotSpot, ? menor do que 4% em sistemas com at? 36 elementos de processamento. O mapeamento de tarefas foi o processo escolhido para atuar no sistema, utilizando as informa??es de temperatura geradas pelo modelo proposto. O mapeamento de tarefas ? o processo de selecionar um elemento de processamento para executar uma determinada tarefa. O n?mero de n?cleos em sistemas multiprocessados, aumenta a complexidade do mapeamento de tarefas. As principais preocupa??es no mapeamento de tarefas em sistemas de grande porte incluem: (i) escalabilidade; (Ii) carga de trabalho din?mica; e (iii) confiabilidade. ? necess?rio distribuir a decis?o de mapeamento em todo o sistema para assegurar a escalabilidade. A carga de trabalho de sistemas multiprocessados pode ser din?mica, ou seja, novas aplica??es podem come?ar a qualquer momento, levando a diferentes cen?rios de mapeamento. Portanto, ? necess?rio executar o processo de mapeamento em tempo de execu??o para suportar carga din?mica de trabalho. A atribui??o de carga de trabalho desempenha um papel importante na confiabilidade do sistema. O desequil?brio de carga pode gerar zonas de hotspot e consequentemente implica??es t?rmicas. Recentemente, t?cnicas de mapeamento de tarefas com o objetivo de melhorar a confiabilidade do sistema foram propostas na literatura. No entanto, tais abordagens dependem de decis?es de mapeamento centralizado, que n?o s?o escal?veis. Para enfrentar esses desafios, esta Tese prop?e uma heur?stica de mapeamento hier?rquico realizado em tempo de execu??o, que ofere?a escalabilidade e uma melhor distribui??o t?rmica. A melhor distribui??o t?rmica dentro do sistema aumenta a confiabilidade do sistema a longo prazo, devido ? redu??o das varia??es t?rmicas e redu??o de zonas de hotspot. A heur?stica de mapeamento proposta considera a temperatura do PE como uma fun??o custo. A proposta adota um esquema hier?rquico de monitoramento de temperatura, capaz de estimar em tempo de execu??o a temperatura instant?nea de cada elemento de processamento. O mapeamento usa a temperatura estimada pelo m?todo de monitoramento para orientar a decis?o de mapeamento. Os resultados comparam a proposta com uma heur?stica de mapeamento cuja principal fun??o de custo minimiza a energia de comunica??o. Os resultados obtidos mostram diminui??o da temperatura m?xima (melhor caso, 8%) e melhora na distribui??o t?rmica (melhor caso, valor 50% menor do desvio padr?o das temperaturas dos processadores). Al?m disso, alcan?ou-se, no melhor caso, um aumento de 45% no tempo de vida do sistema utilizando o mapeamento proposto.

On assiste aujourd’hui au développement massif des technologies nomades. L’utilisation de boîtiers compacts est ainsi en plein croissance, non seulement à cause des téléphones portables et tablettes, mais aussi à cause de l’introduction massive de l’électronique dans les appareils portables de la vie quotidienne. La microélectronique embarquée dans ces appareils représente le principal outil d’information et de communication des personnes avec le monde extérieur. Le rythme de développement de ces technologies dans les dernières années est tel que les possibilités d’utilisation des appareils portables d’aujourd’hui étaient de la science-fiction il y a seulement 10 ans.Les fonctionnalités qui verront le jour dans les années à venir ne peuvent donc pas toutes être encore imaginées. Ces fonctionnalités vont toutefois très certainement impliquer une augmentation des performances de calcul des dispositifs, et par conséquent de la chaleur qu’ils dissipent.Aujourd’hui, on envisage des puces complexes comprenant plusieurs niveaux logiques et basées sur technologies hétérogènes. On demande également que ces technologies soient intégrées dans les appareils utilisés dans la vie quotidienne, qu’ils soient connectés entre eux et qu’ils réagissent de façon intelligente. Les stratégies de dissipation de la chaleur doivent donc être en adéquation avec la réduction des dimensions des dispositifs de la microélectronique.L’objectif de la thèse présentée dans ce manuscrit est ainsi d’étudier les stratégies de dissipation thermique des boîtiers compacts avec l’aide de répartiteurs de chaleur intégrés. Ce travail porte sur la caractérisation des performances et contraintes des répartiteurs thermiques avec matériaux carbonés. Les répartiteurs sont capables de dissiper sur sa surface la chaleur produite dans un point chaud.Afin d’étudier le phénomène de la dissipation avec un répartiteur, on a mis en place une méthodologie qui prend en compte le caractère multiniveau de la dissipation thermique. L’objectif est de pouvoir se concentrer sur l’interaction entre le répartiteur thermique et chacun des éléments de l’ensemble. On a réutilisé deux véhicules de test et on a désigné un véhicule de test spécifique pour l’étude de la thermique des puces imageurs.Les travaux sont basés sur deux axes : Les études d’intégration et les études thermiques. Les études d’intégration prennent en compte les contraintes dérivées de l’implémentation des couches répartiteurs dans des boitiers compactes. On se concentre d’abord sur les procès d’implémentation des couches répartiteurs au sein de l’ensemble dans un procès industriel. Ensuite on étudie les effets thermomécaniques et les effets sur l’intégrité des signaux à haute fréquence.Les études thermiques caractérisent le gain en performances dérivé de cette intégration. On analyse ces phénomènes thermiques avec des mesures et des simulations. Premièrement au niveau silicium et répartiteur, deuxièmement au niveau boitier et finalement on se concentre sur les effets dans une puce et boitier imageur.A la lumière des résultats on peut dire que les matériaux carbonés se présentent comme l’alternative plus intéressante pour l’implémentation à grande échelle de répartiteurs dans des boitiers compacts. Cette implémentation sera poussée par la recherche des prestations dans des boitiers de plus en plus complexes et hétérogènes, ou l’empreinte du répartiteur doit être minimale. La combination des couches de carbone a tous les niveaux du boitier, avec des TIMs des épaisseurs réduites sera la tendance dans les années à venir pour ce type de dispositifs.Cette thèse s’inscrit dans le cadre d’une collaboration tripartie entre le CEA-LETI de Grenoble, le laboratoire G2Elab de l’INP Grenoble et STMicroelectronics à Crolles. / We witness today an explosion of nomadic technologies. Portable devices have become the main tool that people use to connect with the rest of the world. The microelectronics embedded in these devices is the technology that drives this process. The pace of development of these technologies is such that the versatility of portable devices today were science fiction only 10 years ago.The functionalities that will be integrated in the coming years cannot be imagined yet. These features will imply an increase of the computing demands, and consequently, of the heat dissipated inside them. The trend leads to complex stacks with heterogeneous modules of heat dissipating layers.These technologies will be integrated in everyday life. Internet of Things, as we call it, will demand an increasing amount of independent low footprint devices that will be connected. Heat dissipation strategies must therefore be compatible with increasingly smaller dimensions. Compact packages demand is growing rapidly, not only because of telephones and tablets, but also because of the massive introduction of electronics into in everyday life devices.The objective of the thesis is to study the integration of heat-spreaders in compact packages to enhance its thermal performance. This work goes deeply in the characterization of the thermal performance of carbon-base heat spreaders. Heat-spreaders are able to extract the heat produced in hot spots and transport it along its surface.In order to study the heat spreading phenomenon, a methodology that takes into account the multi-level nature of heat dissipation has been implemented. The objective is to be able to focus on the interaction between the heat-spreader and each one of the elements of the package stack. Two test vehicles have been re-used from previous works. A specific test vehicle was also design in order to emulate the thermal behavior of imaging sensors.The thesis is based on two main axes: Integration studies and thermal studies. The integration studies take into account the constraints derived from the implementation of heat spreaders in compact packages. Firstly, we focus on the implementation processes within an industrial process. Latelly, we study the thermomechanical effects of heat spreaders and the impact on the integrity of high frequency signals.Thermal studies are aimed to characterize the performance gain derived from this heat spreader integration. The thermal phenomena are analyzed with measurements and simulations. First at silicon and interface level, then at package level, finally we focus on the effects in image sensor die and package.In the light of the results it can be said that carbon based materials are the most interesting alternative for large-scale implementation of heat spreaders in compact packages. This implementation will be driven by the research of new functionalities and performances in compact packages. The heat spreader will have to perform while maintaining a minimal footprint. The combination of carbon layers at all package levels, along with reduced thermal interface thickness will be the trend in the coming years for this type of device.This thesis is part of a tripartite collaboration between the CEA-LETI of Grenoble, the G2Elab laboratory of the INP Grenoble and STMicroelectronics in Crolles.

High efficiency multi-junction (MJ) solar cells were packaged onto receiver systems. The efficiency change of concentrator cells under continuous high intensity illumination was done. Also, assessment of the receiver design on the overall performance of a Fresnel-type concentration system was investigated. We present on receiver designs including simulation results of their three-dimensional thermal operation and experimental results of tested packaged receivers to understand their efficiency in real world operation. Thermal measurements from solar simulators were obtained and used to calibrate the model in simulations. The best tested efficiency of 36.5% is obtained on a sample A receiver under 260 suns concentration by the XT-30 solar simulator and the corresponding cell operating temperature is ~30.5°C. The optimum copper thickness of a 5 cm by 5 cm simulated alumina receiver design was determined to be 6 mm and the corresponding cell temperature under 1000 suns concentration is ~36°C during operation.

The main goal of this thesis is to develop an active thermal management control scheme for multi-phase current mode buck converters in order to improve the long term reliability of the converters. A thermal management unit (TMU) with independent linear compensators for the thermal loops is incorporated into the existing digital controller to regulate the current through each phase so that equal temperature distribution is achieved across all phases. A lumped parameter thermal model of the multi-phase converter is built as the basis of the TMU. MATLAB simulation results are used to verify the TMU concept. Experimental results from a digitally controlled 12 V to 1 V, 50 A, 250 kHz four-phase peak current mode buck converter demonstrate the effectiveness of the proposed thermal management technique in the presence of uneven air flow. The steady-state performance, dynamic transient load performance, effect of gate drive voltage and efficiency measurements are investigated and discussed.

The main goal of this thesis is to develop an active thermal management control scheme for multi-phase current mode buck converters in order to improve the long term reliability of the converters. A thermal management unit (TMU) with independent linear compensators for the thermal loops is incorporated into the existing digital controller to regulate the current through each phase so that equal temperature distribution is achieved across all phases. A lumped parameter thermal model of the multi-phase converter is built as the basis of the TMU. MATLAB simulation results are used to verify the TMU concept. Experimental results from a digitally controlled 12 V to 1 V, 50 A, 250 kHz four-phase peak current mode buck converter demonstrate the effectiveness of the proposed thermal management technique in the presence of uneven air flow. The steady-state performance, dynamic transient load performance, effect of gate drive voltage and efficiency measurements are investigated and discussed.

Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack. This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm² of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min. The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm².

High efficiency multi-junction (MJ) solar cells were packaged onto receiver systems. The efficiency change of concentrator cells under continuous high intensity illumination was done. Also, assessment of the receiver design on the overall performance of a Fresnel-type concentration system was investigated. We present on receiver designs including simulation results of their three-dimensional thermal operation and experimental results of tested packaged receivers to understand their efficiency in real world operation. Thermal measurements from solar simulators were obtained and used to calibrate the model in simulations. The best tested efficiency of 36.5% is obtained on a sample A receiver under 260 suns concentration by the XT-30 solar simulator and the corresponding cell operating temperature is ~30.5°C. The optimum copper thickness of a 5 cm by 5 cm simulated alumina receiver design was determined to be 6 mm and the corresponding cell temperature under 1000 suns concentration is ~36°C during operation.