Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.

Multi-chip integration with emerging technologies such as a 3D IC stack or 2.5D interposer is primarily enabled by the off-chip interconnections. The I/O density, speed and bandwidth requirements for emerging mobile and high-performance systems are projected to drive the interconnection pitch to less than 20 microns by 2015. A new class of low-temperature, low-pressure, high-throughput, cost-effective and maufacturable technologies are needed to enable such fine-pitch interconnections. A range of interconnection technologies are being pursued to achieve these fine-pitch interconnections, most notably direct Cu-Cu interconnections and copper pillars with solder caps. Direct Cu-Cu bonding has been a target in the semiconductor industry due to the high electrical and thermal conductivity of copper, its high current-carrying capability and compatibility with CMOS BEOL processes. However, stringent coplanarity requirements and high temperature and high pressure bonding needed for assembly have been the major barriers for this technology. Copper-solder interconnection technology has therefore become the main workhouse for off-chip interconnections, and has recently been demonstrated at pitches as low as 40 microns. However, the current interconnection approaches using copper-solder structures are not scalable to finer feature sizes due to electromigration, and reliability issues arising with decreased solder content. Solid Liquid Inter-Diffusion (SLID) bonding is a promising solution to achieve ultra-fine-pitch and ultra-short interconnections with a copper-solder system, as it relies on the conversion of the entire solder volume into thermally-stable and highly electromigration-resistant intermetallics with no residual solder. Such a complete conversion of solders to stable intermetallics, however, relies on a long assembly time or a subsequent post-annealing process. To achieve pitches lower than 30 micron pitch, this research aims to study two ultra-short copper-solder interconnection approaches: (i) copper pillar and solder cap technology, and (ii) a novel technology which will enable interconnections with improved electrical performance by fast and complete conversion of solders to stable intermetallics (IMCs) using Solid Liquid Diffusion (SLID) bonding approach. SLID bonding, being a liquid state diffusion process, combined with a novel, alternate layered copper-solder bump structure, leads to higher diffusion rates and a much faster conversion of solder to IMCs. Moreover this assembly bonding is done at a much lower temperature and pressure as compared to that used for Cu-Cu interconnections. FEM was used to study the effect of various assembly and bump-design characteristics on the post-assembly stress distribution in the ultra-short copper-solder joints, and design guidelines were evolved based on these results. Test vehicles, based on these guidelines, were designed and fabricated at 50 and 100 micron pitch for experimental analysis. The bumping process was optimized, and the effect of current density on the solder composition, bump-height non-uniformity and surface morphology of the deposited solder were studied. Ultra-short interconnections formed using the copper pillar and solder cap technology were characterized. A novel multi-layered copper-solder stack was designed based on diffusion modeling to optimize the bump stack configuration for high-throughput conversion to stable Cu3Sn intermetallic. Following this modeling, a novel bumping process with alternating copper and tin plating layers to predesigned thicknesses was then developed to fabricate the interconnection structure. Alternate layers of copper and tin were electroplated on a blanket wafer, as a first demonstration of this stack-technology. Dies with copper-solder test structures were bonded using SLID bonding to validate the formation of stable intermetallics.

We have developed a placement-aware 3-D floorplanning algorithm that enables additional wirelength reduction by planning for 3-D placement of logic gates in selected circuit modules during the floorplanning stage. Thus it also bridges the existing gap between 3-D floorplanning and 3-D placement. To reduce the solution space of 3-D floorplanning which is known to be an NP-hard problem, we derive a set of feasibility conditions on the topological representation of a floorplan. In addition, we have designed a fast module packing algorithm that satisfies a set of constraints for placement-aware 3-D floorplanning. Furthermore, we have designed an efficient evolutionary algorithm that is used in the proposed 3-D floorplanning algorithm for multi-objective combinatorial optimization. Our results show that the proposed placement-aware 3-D floorplanning algorithm is very fast, and it reduces the system level total wirelength by 9.8% compared to existing state-of-the-art floorplanning tools that do not plan for 3-D placement of floorplanning modules.

The continuous miniaturization of electronic systems using the three-dimensional (3D) integration technique has brought in new challenges for the computer-aided design and modeling of 3D integrated circuits (ICs) and systems. The major challenges for the modeling and analysis of 3D integrated systems mainly stem from four aspects: (a) the interaction between the electrical and thermal domains in an integrated system, (b) the increasing modeling complexity arising from 3D systems requires the development of multiscale techniques for the modeling and analysis of DC voltage drop, thermal gradients, and electromagnetic behaviors, (c) efficient modeling of microfluidic cooling, and (d) the demand of performing fast thermal simulation with varying design parameters. Addressing these challenges for the electrical/thermal modeling and analysis of 3D systems necessitates the development of novel numerical modeling methods. This dissertation mainly focuses on developing efficient electrical and thermal numerical modeling and co-simulation methods for 3D integrated systems. The developed numerical methods can be classified into three categories. The first category aims to investigate the interaction between electrical and thermal characteristics for power delivery networks (PDNs) in steady state and the thermal effect on characteristics of through-silicon via (TSV) arrays at high frequencies. The steady-state electrical-thermal interaction for PDNs is addressed by developing a voltage drop-thermal co-simulation method while the thermal effect on TSV characteristics is studied by proposing a thermal-electrical analysis approach for TSV arrays. The second category of numerical methods focuses on developing multiscale modeling approaches for the voltage drop and thermal analysis. A multiscale modeling method based on the finite-element non-conformal domain decomposition technique has been developed for the voltage drop and thermal analysis of 3D systems. The proposed method allows the modeling of a 3D multiscale system using independent mesh grids in sub-domains. As a result, the system unknowns can be greatly reduced. In addition, to improve the simulation efficiency, the cascadic multigrid solving approach has been adopted for the voltage drop-thermal co-simulation with a large number of unknowns. The focus of the last category is to develop fast thermal simulation methods using compact models and model order reduction (MOR). To overcome the computational cost using the computational fluid dynamics simulation, a finite-volume compact thermal model has been developed for the microchannel-based fluidic cooling. This compact thermal model enables the fast thermal simulation of 3D ICs with a large number of microchannels for early-stage design. In addition, a system-level thermal modeling method using domain decomposition and model order reduction is developed for both the steady-state and transient thermal analysis. The proposed approach can efficiently support thermal modeling with varying design parameters without using parameterized MOR techniques.