Ethernet Switches are widely used in real-time distributed systems as a solution to guarantee the real-time behavior in communication. In this solution there are still some limitations which are the important obstacles obtaining timeliness in the network. These limitations are the limited number of priority levels as well as the possibility of memory overruns with consequent messages. The mentioned limitations can be eliminated using a master/slave technique along with FTT paradigm. The FTT-SE protocol which is a technique based on the master/slave and FTT methods was proposed to overcome the mentioned limitations. However, the FTT-SE protocol has been investigated for a small network architecture with a single switch and master node. Extension of this solution to larger networks is still an open issue. Three different architectures were suggested to scale the FTT-SE to large scale network. In this thesis we propose a solution that extends the FTT-SEprotocol while keeping the real-time behavior of the network. In this solution, we divided the network into a set of sub-networks, each contains one switch, set of slave nodes and one master node that connected to the associated switch in the network. Moreover, the switches are connected together directly without gateways and form a tree topology network. The solution includes both synchronous and asynchronous traffic in the network. We also show that the timeliness of the traffic can still be enforced. Moreover, to validate the solution we have designed and implemented a simulator based on the Matlab/Simulink which is a tool to evaluate different network architecture using Simulink blocks. All transmission can be visualized by the ordinary Scope block in the Simulink. Moreover, the end-to-end delay for all messages is calculated after the simulation running to show the response time of the network. Furthermore, the response time analysis is done for both synchronous and asynchronous messages in this thesis according to the proposed solution. The results from simulation and the analysis are compared together to validate the investigations.

Embedded computer systems are used as control systems in many products, such as VCRs, digital cameras, washing machines, automobiles, airplanes, etc. As the complexity of embedded applications grows and time-to-market of the products they are used in reduces, designing reliable systems satisfying multiple require-ments is a great challenge. Successful design, nowadays, cannot be performed without good design tools based on powerful design methodologies. These tools should explore different design alternatives to find the best one and do that at high abstraction levels to manage the complexity and reduce the design time. A design is specified using models. Different models are used at different de-sign stages and abstraction levels. For example, the functionality of an application can be specified using hierarchical functional blocks. However, for such design tasks as mapping and scheduling, a lower-level flat model of interacting processes is needed. Deriving this model from a higher-level model of functional blocks is the main focus of this thesis. Our objective is to develop efficient strategies for such derivations, aiming at producing a process graph specification, which helps the synthesis tasks to find schedulable implementations. We proposed several strategies and evaluated them experimentally.

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Day by day, we are witnessing a considerable increase in number and range of applications which entail the use of embedded computer systems. This increase is closely followed by the growth in complexity of applications controlled by embedded systems, often involving strict timing requirements, like in the case of safety-critical applications. Efficient design of such complex systems requires powerful and accurate tools that support the designer from the early phases of the design process. This thesis focuses on the study of real-time distributed embedded systems and, in particular, we concentrate on a certain aspect of their real-time behavior and implementation: the time-triggered (TT) and event-triggered (ET) nature of the applications and of the communication protocols. Over the years, TT and ET systems have been usually considered independently, assuming that an application was entirely ET or TT. However, nowadays, the growing complexity of current applications has generated the need for intermixing TT and ET functionality. Such a development has led us to the identification of several interesting problems that are approached in this thesis. First, we focus on the elaboration of a holistic schedulability analysis for heterogeneous TT/ET task sets which interact according to a communication protocol based on both static and dynamic messages. Second, we use the holistic schedulability analysis in order to guide decisions during the design process. We propose a design optimisation heuristic that partitions the task-set and the messages into the TT and ET domains, maps and schedules the partitioned functionality, and optimises the communication protocol parameters. Experiments have been carried out in order to measure the efficiency of the proposed techniques.

Time-Triggered Controller Area Network (TTCAN) is a hybrid communication paradigm with combining both time-triggered and event-triggered traffic scheduling. Different from the standard Controller Area Network (CAN), communication in TTCAN is performed according to a pre-computed, fixed (during system run) schedule that is called as TTCAN System Matrix. Thus, communication performance of TTCAN network is directly related to structure of the system matrix, which makes the design of system matrix a crucial process. The study in this thesis consists of the extended work on the development of a systematic approach for system matrix construction. Methods for periodic message scheduling and an approach for aperiodic message scheduling are proposed with the aim of constructing a feasible system matrix, combining three important aspects: message properties, protocol constraints and system performance requirements in terms of designated performance metrics. Also, system matrix design, analyses and performance evaluation are performed on example message sets with the help of two developed software tools.

The Electric/Electronic architecture of vehicle becomes more complex and costly, self-adaption can reduce the system, enhance the adaptive meanwhile reduce energy consumption and costs. The self-adaption needs the cooperation of both hardware and software reconfigurations, such that after the software is reconfigured the automotive network continues to fulfill the time constraints for time-critical applications. The thesis focuses on the real-time network reconfiguration. It uses EAST-ADL to model a real-time automotive system with timing events and constraints, which conforms to AUTOSAR timing extensions. The network media access is analyzed based on the model and a scheduling algorithm is developed. Then the concept is implemented by a use case, which is transformed from an EAST-ADL model to an executable simulation.

The Electric/Electronic architecture of vehicle becomes more complex and costly, self-adaption can reduce the system, enhance the adaptive meanwhile reduce energy consumption and costs. The self-adaption needs the cooperation of both hardware and software reconfigurations, such that after the software is reconfigured the automotive network continues to fulfill the time constraints for time-critical applications. The thesis focuses on the real-time network reconfiguration. It uses EAST-ADL to model a real-time automotive system with timing events and constraints, which conforms to AUTOSAR timing extensions. The network media access is analyzed based on the model and a scheduling algorithm is developed. Then the concept is implemented by a use case, which is transformed from an EAST-ADL model to an executable simulation.:1. Introduction 2. Research Fundamentals 2.1. AUTOSAR Specifications for Modeling Function Communication 2.2. Media Access Control in Real-time Network 3. Function Communication Model and Determination of Network Configuration 3.1. Function Communication Model 3.2. Scheduling Algorithm for Media Access 4. Implementation of Communication Model and Plugin for Model Transformation 4.1. EAST-ADL Modeling Language 4.2. Implementation of Function Communication Model in EAST-ADL 4.3. Model Transformation Plugin and Simulation Tool Integration 5. Evaluation of the Function Communication Model 5.1. Use-Case Model for Evaluation 5.2. Time Values of Use-Case Model 5.3. Analysis and Evaluation of Simulation Result 6. Conclusion and Outlook 6.1. Conclusion of the Work 6.2. Outlook of the Future Work A. OMNeT++ Simulation Log B. EAST-ADL Model to Artop Model Mapping Bibliography Nomenclature

Les travaux réalisés dans le cadre de cette thèse ont pour objectif de proposer un langage de description temporelle pour des systèmes temps-réel et d’établir les conditions de leur ordonnançabilité sous l’algorithme Earliest Deadline First (EDF). Les langages de description temporelle permettent de spécifier le comportement temporel d’une application indépendamment de son comportement fonctionnel. Le programmeur déclare dans ces langages à quels instants précis doivent être déclenchées et terminées les activités du système. Cette gestion du temps, précise et explicite, apporte au système son caractère déterministe. Le langage proposé, Extended Timing Definition Language (E-TDL), étend des langages dirigés par le temps existants, en particulier Giotto et TDL, en introduisant un nouveau modèle de tâche donné par quatre paramètres : phase, pire temps d’exécution, temps d’exécution logique TEL (intervalle de temps séparant le lancement de la tâche et sa terminaison) et période. L’introduction de ce nouveau modèle de tâche nécessite de revisiter en particulier le problème de l’ordonnançabilité des tâches pour EDF. Cette thèse propose et développe une analyse basée sur la fonction de demande pour des ensembles de tâches décrites en E-TDL et s’exécutant en contexte monoprocesseur. Une condition nécessaire et suffisante est obtenue au travers d’une analyse précise des intervalles séparant les activations de tâches au sein de différents modules s’exécutant indépendamment et pouvant changer de mode à des instants prédéfinis. Une borne de la longueur des intervalles sur lesquels doit s’opérer la vérification est déterminée. Un outil mettant en œuvre cette analyse a été développé. / The goal of this research is to define a time-triggered language for modeling real-time systems and to provide the conditions for their schedulability under Earliest Deadline First (EDF). Time-triggered languages separate the functional part of applications from their timing definition. These languages permit to model the real-time system temporal behavior by assigning system activities to particular time instants. We propose a new time-triggered framework, Extended Timing Definition Language (E-TDL), that enhances the basic task model used in Giotto and TDL while keeping compositional and modular structure brought by the latter. An E-TDL task is characterized by: an offset, a worst case execution time, a Logical Execution Time (a time interval between task release and its termination) and a period. The schedulability analysis of the system based on this new task model should be, in particular for EDF, investigated. We develop, on the concept of the processor demand criterion, conditions for the feasibility of an E-TDL system running on a single CPU under EDF. A necessary and sufficient condition is obtained by considering the global schedules that are made up of execution traces occurring at the same time in distinct modules that are able to switch their modes at predefined instants. We estimate a maximal length of the interval on which the schedulability condition must be checked. A tool suite performing the schedulability analysis of the E-TDL systems is developed.

Cette thèse traite de systèmes embarqués contrôlés par un ensemble de processus périodiques non synchronisés. Chaque processus est activé quasi-périodiquement, c'est-à-dire périodiquement avec une gigue bornée. Les délais de communication sont également bornés. De tels systèmes réactifs, appelés 'quasi-périodiques', apparaissent dès que l'on branche ensemble deux processus périodiques. Dans la littérature, ils sont parfois qualifiés de systèmes distribués temps-réels synchrones. Nous nous intéressons aux techniques de conception et d'analyse de ces systèmes qui n'imposent pas de synchronisation globale. Les langages synchrones ont été introduits pour faciliter la conception des systèmes réactifs. Ils offrent un cadre privilégié pour programmer, analyser, et vérifier des systèmes quasi-périodiques. En s'appuyant sur une approche synchrone, les contributions de cette thèse s'organisent selon trois thématiques: vérification,implémentation, et simulation des systèmes quasi périodiques.Vérification: 'L'abstraction quasi-synchrone' est une abstraction discrète proposée par Paul Caspi pour vérifier des propriétés de sûreté des systèmes quasi-périodiques. Nous démontrons que cette abstraction est en général incorrecte et nous donnons des conditions nécessaires et suffisantes sur le graphe de communication et les caractéristiques temps-réel de l'architecture pour assurer sa correction. Ces résultats sont ensuite généralisés aux systèmes multi-périodiques.Implémentation: Les 'LTTAs' sont des protocoles conçus pour assurer l'exécution correcte d'une application sur un système quasi-périodique. Nous proposons d'étudier les LTTA dans un cadre synchrone unifié qui englobe l'application et les contrôleurs introduits par les protocoles. Cette approche nous permet de simplifier les protocoles existants, de proposer des versions optimisées, et de donner de nouvelles preuves de correction. Nous présentons également dans le même cadre un protocole fondé sur une synchronisation d'horloge pour comparer les performances des deux approches.Simulation: Un système quasi-périodique est un exemple de modèle faisant intervenir des caractéristiques temps-réels et des tolérances. Pour ce type de modèle non déterministe, nous proposons une 'simulation symbolique', inspirée des techniques de vérification des automates temporisés. Nous montrons comment compiler un modèle mêlant des composantes temps-réel non déterministes et des contrôleurs discrets en un programme discret qui manipule des ensembles de valeurs. Chaque trace du programme résultant capture un ensemble d'exécutions possibles du programme source. / In this thesis we study embedded controllers implemented as sets of unsynchronized periodic processes. Each process activates quasi-periodically, that is, periodically with bounded jitter, and communicates with bounded transmission delays. Such reactive systems,termed 'quasi-periodic', exist as soon as two periodic processes areconnected together. In the distributed systems literature they arealso known as synchronous real-time models. We focus on techniquesfor the design and analysis of such systems without imposing a globa lclock synchronization. Synchronous languages were introduced as domain specific languages for the design of reactive systems. They offer an ideal framework to program, analyze, and verify quasi-periodic systems. Based on a synchronous approach, this thesis makes contributions to the treatment of quasi-periodic systems along three themes: verification,implementation, and simulation.Verification: The 'quasi-synchronous abstraction' is a discrete abstraction proposed by Paul Caspi for model checking safety properties of quasi-periodic systems. We show that this abstractionis not sound in general and give necessary and sufficient conditionson both the static communication graph of the application and the real-time characteristics of the architecture to recover soundness. We then generalize these results to multirate systems.Implementation: 'Loosely time-triggered architectures' are protocols designed to ensure the correct execution of an application running on a quasi-periodic system. We propose a unified framework that encompasses both the application and the protocol controllers. This framework allows us to simplify existing protocols, propose optimized versions, and give new correctness proofs. We instantiate our framework with a protocol based on clock synchronization to compare the performance of the two approaches.Simulation: Quasi-periodic systems are but one example of timed systems involving real-time characteristics and tolerances. For such nondeterministic models, we propose a 'symbolic simulation' scheme inspired by model checking techniques for timed automata. We show how to compile a model mixing nondeterministic continuous-time and discrete-time dynamics into a discrete program manipulating sets of possible values. Each trace of the resulting program captures a set of possible executions of the source program.

La inyección de fallos es una técnica utilizada para la validación experimental de Sistemas Tolerantes a Fallos. Se distinguen tres grandes categorías: inyección de fallos física (denominada también physical fault injection o hardware implemented fault injection), inyección de fallos implementada por software (en inglés software implemented fault injection) e inyección de fallos basada en simulación. Una de las que más auge está teniendo últimamente es la inyección de fallos basada en simulación, y en particular la inyección de fallos basada en VHDL. Las razones del uso de este lenguaje se pueden resumir en: " Es un lenguaje estándar ampliamente utilizado en el diseño digital actual. " Permite describir el sistema en distintos niveles de abstracción. " Algunos elementos de su semántica pueden ser utilizados en la inyección de fallos. Para realizar la inyección de fallos basada en VHDL, diferentes autores han propuesto tres tipos de técnicas. La primera está basada en la utilización de los comandos del simulador para modificar los valores de las señales y variables del modelo. La segunda se basa en la modificación del código, insertando perturbadores en el modelo o creando mutantes de componentes ya existentes. La tercera técnica se basa en la ampliación de los tipos del lenguaje y en la modificación de las funciones del simulador VHDL. Actualmente, ha surgido otra tendencia de la inyección de fallos basada en VHDL, denominada genéricamente emulación de fallos. La emulación añade ciertos componentes al modelo (inyectores, que suelen ser perturbadores o mutantes, disparadores de la inyección, recolectores de datos, etc.). El modelo junto con los nuevos componentes son sintetizados en una FPGA, que es donde se realiza la inyección. Con la introducción cada vez mayor de sistemas tolerantes a fallos en aplicaciones críticas, su validación se está convirtiendo en uno de los puntos clave para su uso. / Gracia Morán, J. (2004). Validación por inyección de fallos en VHDL de la arquitectura TTA [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/7526 / Palancia