While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

The objective of this research is to explore high-speed analog-to-digital converters (ADCs) using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for wireless digital receiver applications. The stringent requirements of ADCs for the high-performance next-generation wireless digital receiver include (1) low power, (2) low cost, (3) wide input signal bandwidth, (4) high sampling rate, and (5) medium to high resolution. The proposed research achieves the objective by implementing high-performance ADC's key building blocks and integrating these building blocks into a complete sigma-delta analog-to-digital modulator that satisfies the demanding specifications of next-generation wireless digital receiver applications. The scope of this research is divided into two main parts: (1) high-performance key building blocks of the ADC, and (2) high-speed sigma-delta analog-to-digital modulator. The research on ADC's building blocks includes the design of two high-speed track-and-hold amplifiers (THA) and two wide-bandwidth comparators operating at the sampling rate > 10 GS/sec with satisfying resolution. The research on high-speed sigma-delta analog-to-digital modulator includes the design and experimental characterization of a high-speed second-order low-pass sigma-delta modulator, which can operate with a sampling rate up to 20 GS/sec and with a medium resolution. The research is envisioned to demonstrate that the SiGe HBT technology is an ideal platform for the design of high-speed ADCs.

Les communications futures pour les applications civiles et militaires utilisent des signaux modulés complexes large bande qui seront émis à travers des amplificateurs de puissance multivoie de type DOHERTY qui devront avoir des performances en puissance, rendement, OBO et largeur de bande qui constituent aujourd’hui un véritable défi à relever. Pour ce faire les concepteurs ont besoin d’outils de caractérisation temporelle permettant la mesure normalisées et l’optimisation des tensions et courants aux accès des dispositifs non linéaires sous pointes ou connectorisés. Ce travail de thèse a permis de mettre en œuvre cet outil de caractérisation temporelle qui a été utilisé pour répondre à des besoins spécifiques pour la modélisation de transistor, pour l’optimisation de leur fonctionnement en termes de stabilité impulsion à impulsion, pour la recherche des conditions optimales de leur fonctionnement dans un amplificateur de type Doherty. Pour cette mise en œuvre une modélisation mathématique des échantillonneurs a été réalisée pour évaluer leurs performances et choisir le mieux adapté à la mesure temporelle RF. Des procédures d’étalonnages rigoureuses ont été développées pour obtenir simultanément des formes d’ondes temporelles calibrées à spectre très large (Basse fréquences jusqu’aux Hyperfréquences). / The future communications for civil and military applications will use complex wideband modulated signals to be transmitted through multi-channel DOHERTY power amplifiers which should have high performance in terms of power, efficiency, OBO, and bandwidth. In order to meet these stringent requirements, designers need time-domain characterization tools for calibrated measurements and for optimizing voltages and currents at both ports of non-linear connectorized or on-wafer devices. This work successfully implements time-domain characterization tools used to meet specific needs for transistor modeling, to optimize their operation in terms of pulse to pulse stability, and to search optimal conditions of their operation modes in a Doherty power amplifier. For this implementation, mathematical modeling is performed to evaluate sampler’s performances in terms of time-domain sampling efficiency in order to choose the best suited sampling architecture for RF time-domain measurements. Rigorous calibration procedures have been developed to obtain simultaneously full time-domain calibrated waveforms (from low Frequencies to Microwave frequencies).

Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquence. / This thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation.