The combination of silicon photonics and advanced heterogeneous integration is promising for next-generation disaggregated data centers that demand large scale, high throughput, and low power. In this dissertation, we discuss the design and theory of power-efficient optical transceivers with System-in-Package (SiP) 2.5D integration. Combining prior arts and proposed circuit techniques, a receiver chip and a transmitter chip including two 10 Gb/s data channels and one 2.5 GHz clocking channel are designed and implemented in 28 nm CMOS technology. An innovative transimpedance amplifier (TIA) and a single-ended to differential (S2D) converter are proposed and analyzed for a low-voltage high-sensitivity receiver; a four-to-one serializer, programmable output drivers, AC coupling units, and custom pads are implemented in a low-power transmitter; an improved quadrature locked loop (QLL) is employed to generate accurate quadrature clocks. In addition, we present an analysis for inverter-based shunt-feedback TIA to explicitly depict the trade-off among sensitivity, data rate, and power consumption. At last, the research on CDR-based​ clocking schemes for optical links is also discussed. We introduce prior arts and propose a power-efficient clocking scheme based on an injection-locked phase rotator. Next, we analyze injection-locked ring oscillators (ILROs) that have been widely used for quadrature clock generators (QCGs) in multi-lane optical or wireline transceivers due to their low power, low area, and technology scalability. The asymmetrical or partial injection locking from 2 phases to 4 phases results in imbalances in amplitude and phase. We propose a modified frequency-domain analysis to provide intuitive insight into the performance design trade-offs. The analysis is validated by comparing analytical predictions with simulations for an ILRO-based QCG in 28 nm CMOS technology. This dissertation also discusses the design of high-linearity wireless wideband receivers. An out-of-band (OB) IM3 cancellation technique is proposed and analyzed. By exploiting a baseband auxiliary path (AP) with a high-pass feature, the in-band (IB) desired signal and out-of-band interferers are split. OB third-order intermodulation products (IM3) are reconstructed in the AP and cancelled in the baseband (BB). A 0.5-2.5 GHz frequency-translational noise-cancelling (FTNC) receiver is implemented in 65nm CMOS to demonstrate the proposed approach. It consumes 36 mW without cancellation at 1 GHz LO frequency and 1.2 V supply, and it achieves 8.8 MHz baseband bandwidth, 40dB gain, 3.3dB NF, 5dBm OB IIP3, and −6.5dBm OB B1dB. After IM3 cancellation, the effective OB-IIP3 increases to 32.5 dBm with an extra 34 mW for narrow-band interferers (two tones). For wideband interferers, 18.8 dB cancellation is demonstrated over 10 MHz with two −15 dBm modulated interferers. The local oscillator (LO) leakage is −92 dBm and −88 dB at 1 GHz and 2 GHz LO respectively. In summary, this technique achieves both high OB linearity and good LO isolation.

The objective of our research is to develop system architectures and CMOS circuits that interface with high-Q silicon microgyroscopes to implement navigation-grade angular rate sensors. The MEMS sensor used in this work is an in-plane bulk-micromachined mode-matched tuning fork gyroscope (M² – TFG ), fabricated on silicon-on-insulator substrate. The use of CMOS transimpedance amplifiers (TIA) as front-ends in high-Q MEMS resonant sensors is explored. A T-network TIA is proposed as the front-end for resonant capacitive detection. The T-TIA provides on-chip transimpedance gains of 25MΩ, has a measured capacitive resolution of 0.02aF /√Hz at 15kHz, a dynamic range of 104dB in a bandwidth of 10Hz and consumes 400μW of power. A second contribution is the development of an automated scheme to adaptively bias the mechanical structure, such that the sensor is operated in the mode-matched condition. Mode-matching leverages the inherently high quality factors of the microgyroscope, resulting in significant improvement in the Brownian noise floor, electronic noise, sensitivity and bias drift of the microsensor. We developed a novel architecture that utilizes the often ignored residual quadrature error in a gyroscope to achieve and maintain perfect mode-matching (i.e.0Hz split between the drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS implementation is developed that allows mode-matching of the drive and sense frequencies of a gyroscope at a fraction of the time taken by current state of-the-art techniques. Further, this mode-matching technique allows for maintaining a controlled separation between the drive and sense resonant frequencies, providing a means of increasing sensor bandwidth and dynamic range. The mode-matching CMOS IC, implemented in a 0.5μm 2P3M process, and control algorithm have been interfaced with a 60μm thick M2−TFG to implement an angular rate sensor with bias drift as low as 0.1°/hr ℃ the lowest recorded to date for a silicon MEMS gyro.

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