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Les semiconducteurs III-V antimoniés suscitent un intérêt grandissant pour les applications électroniques rapides et faible consommation. Ces matériaux de paramètre de maille supérieur à 6,1 Å se caractérisent par des mobilités élevées et offrent une souplesse inégalée pour l’ingénierie des bandes. En particulier, le composé ternaire GaInSb se pose comme un candidat de choix pour la base des transistors bipolaires à hétérojonction du fait de sa haute mobilité de trous. L’objectif de cette thèse est d’évaluer la faisabilité et les potentialités d’une nouvelle filière de TBH à base d’antimoine en s’appuyant sur des hétérostructures originales AlIn(As)Sb/GaInSb. La réalisation de composants dans ce système moins bien connu que les systèmes plus classiques InP/InGaAs ou InP/GaAsSb a nécessité le développement de briques technologiques propres. L’étude de solutions de gravure pour la réalisation des mesa a notamment été entreprise et a permis d’identifier de nouvelles solutions chimiques adaptées à la gravure sélective de ces matériaux. Une attention particulière a également été portée sur la minimisation des résistivités spécifiques de contact qui a permis de dégager les paramètres critiques à l’obtention de contacts ohmiques de bonne qualité sur les couches en GaInSb de types n et p. La technologie développée a rendu possible la fabrication de dispositifs présentant des fréquences de coupure fT de 52 GHz et fMAX de 48 GHz. La caractérisation électrique précise tant en régime statique que dynamique des composants fabriqués ainsi que l’extraction du modèle petit signal nous ont permis de déterminer les principales limitations de ces dispositifs. / The so-called ABCS (antimonide-based compound semiconductor) materials have a great potential for low power, high speed electronics as they have high electron and hole mobilities and provide a unique opportunity for bandgap engineering. The ternary material GaInSb has specifically recently emerged as a good candidate for the base layer of high performance heterojunction bipolar transistors (HBT). The purpose of this work is to demonstrate the feasibility and potentialities of a new antimonide-based HBT structure using AlIn(As)Sb/GaInSb heterojunctions. The fabrication of devices in this material system represents a new technological approach as compared to the conventional InP/GaInAs or InP/GaAsSb HBTs and has necessitated the development of various processing steps. In this study, we have investigated new selective chemical solutions to expose the base and the subcollector surface, as well as for achieving device isolation. High quality and reliable ohmic contacts has also been explored by investigating the factors that influence the specific contact resistivity, thermal stability, and shallowness of the ohmic contacts to n- and p-GaInSb. The fabricated devices demonstrated good microwave behaviour with a current gain cutoff frequency fT of 52 GHz and a maximum oscillation frequency fMAX of 48 GHz. Electrical analysis based on dc and RF measurements and a small signal equivalent circuit model enabled the determination of the limiting factors that need to be addressed for further improvement.

The exponential characteristic of the base-emitter Junction in bipolar transistors was used to make an accurate and fairly temperature independent multiplier. Using hybrid-pi transistor models and ECAP, a bandwidth of 350 MHz was predicted. Linearity is limited by emitter degeneration in the input differential stage rather than by the small errors in the actual multiplying stage. The multiplier was fabricated as a monolithic integrated circuit in the Tektronix integrated circuits laboratory. The prototype showed a bandwidth of 200 MHz, and a linearity of 2% over 50% of the dynamic range, when used as a variable gain amplifier. / Graduation date: 1968

In this thesis, we will investigate the degradation of the Low-Temperature-Polycrystalline-Silicon TFTs(LTPS TFTS) under the electrical stress. The devices are offer by Chi Mei Optoelectronics. The two mechanisms of the electrical stress are ac and dc stress. On the dc stress, we can separate the two degradation mechanisms from fixed drain voltage and various the gate voltage. The first mechanism is hot carrier effect, and second is self-heating effect. We were study the degradation mechanisms cause by above-mentioned phenomenon. On the other hand, we were confirmed the position and type of the defects by measured capacitance. In the ac stress, device degradation depends on the emission rate and energy of the hot carrier. We will study the degradation mechanism which fixed the drain voltage and various the Vg_low and falling time under different temperature. Another way of the ac stress condition will be used here. The drain and source are directly connected to ground. The gate is directly connected to the pulse. At this stress condition, carrier will push to the junction near the drain and source when gate pulse is switch from high to low. This degradation mechanism is the function of the temperature. We are going to employ a C-V measurement to examination of the defect cause by stress.

Tri-state structures are used to implement multiplexers and buses because these structures are faster than AND/OR logic structures. But testing of tri-state structures has some issues associated with it. A stuck open control line of a tri-state gate will cause some lines in the circuit to float and take unknown values. A stuck-on control line can cause fighting when the two drivers connected to the same node drive different values. This thesis develops new gate level fault models and dynamic test patterns that take care of these problems. The models can be used with traditional stuck-at and transition fault automatic test pattern generation (ATPG) to ensure high fault coverage. This research focuses on producing good test coverage with reduced effort for tristate and pass transistor structures. We do circuit level modeling to help develop and validate gate level models, which can be used in production ATPG. We study the two primary effects of interest, capacitive coupling and leakage, and analyze the tri-state structures using these two effects. Coupling and leakage can cause a Z or X state to be seen as 0 or 1 in some cases. We develop parameterized models of behavior of common structures using these effects and some parameters such as number of fan-ins. We also develop gate level models of tri-state circuits that would replace the tri-state library cells in the ATPG engine. This work develops a methodology to make tri-state and pass transistor circuit structures more usable in the industry.

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