No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

Submitted by Irene Nascimento (irene.kessia@ufpe.br) on 2017-03-21T19:41:42Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) DISSERTAÇÃO MALANA FINAL.pdf: 2413280 bytes, checksum: 40727bc7ff951331cb16c7c787dd0919 (MD5) / Made available in DSpace on 2017-03-21T19:41:43Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) DISSERTAÇÃO MALANA FINAL.pdf: 2413280 bytes, checksum: 40727bc7ff951331cb16c7c787dd0919 (MD5) Previous issue date: 2016-07-28 / Capes / Transistores bipolares de junção - TBJ possuem uma característica inerente à sua construção física que é o fator de amplificação do sinal produzido, ou seja, amplificação da corrente. Fótons de megavoltagem, ao interagirem com o material semicondutor são capazes de produzir o que é chamado de fotocorrente, ao mesmo tempo em que provocam danos na estrutura cristalina do transistor. O objetivo desta dissertação foi caracterizar o TBJ do tipo BC846 para feixes de fótons de megavoltagem com a finalidade de entender o comportamento deste dispositivo para que futuramente seja desenvolvido um novo método dosimétrico visando complementar os métodos já existentes. O estudo concerniu em caracterizar um TBJ para se analisar como tal dispositivo eletrônico pode ser utilizado como detector de radiação no modo ativo, isto é, em mensurar em tempo real a dose, taxa de dose, dependência energética, e os efeitos direcional e de tamanho de campo de irradiação. Os experimentos foram realizados utilizando um simulador de placas de água sólida com o transistor posicionado no eixo central do feixe em uma profundidade de 5 cm, tamanho de campo padrão, 10 x 10 cm², e uma distância fonte-superfície de 100 cm. Os resultados mostram que o TBJ pode funcionar como detector em feixes de radioterapia desde que seja obedecido certos critérios técnicos relacionados ao comportamento elétrico do dispositivo antes e durante a irradiação. Uma perda percentual média de ±3% na sensibilidade do dispositivo foi registrada após cada irradiação. Essa variação guarda uma proporcionalidade com a dose absorvida e foi encontrada resposta semelhante mesmo com transistores que possuem diferentes fatores de amplificação da corrente. / Bipolar Junction Transistor - BJT have a characteristic inherent to their physical construction, which is the amplification factor of the produced signal, i.e., current amplification. Megavoltage photons interacting with the semiconductor material are capable of producing what is called photocurrent, while causing damage to the crystalline structure of the transistor. The aim of this work was to characterize the BJT type BC846 for MV photon beams in order to understand the behavior of this mechanism to be developed in the future a new dosimetric method to complement existing methods. The study's concerned characterization of a BJT to be analyzed as such electronic device may be used as a radiation detector in the active mode, i.e., measuring in real time the dose, dose rate, energy dependence, and directional effects and size radiation field. The experiments were performed using a solid water phantom with the transistor positioned at the central axis of the beam at a depth of 5 cm, standard field size, 10 x 10 cm², and a source-surface distance of 100 cm. The results show that the BJT may function as a detector in radiotherapy beam since certain technical criteria are met related to the electrical behavior of the device before and during the irradiation. An average percentage loss of ± 3% in the device sensitivity was recorded after each irradiation. This variation is in proportion to the dose absorbed and one can see similar response even with transistors having different amplification factors of the current.

La vie dans la société contemporaine a changé énormément depuis l’invention du premier transistor électronique en 1947. L’apparition des transistors a permis la miniaturisation de systèmes électroniques de toute sorte dont la performance des transistors est aussi un aspect essentiel. Présentement, dans les marchés de semi-conducteurs à forte puissance et dans le secteur des technologies de l’information et des communications (TIC), les transistors GaN (Eg = 3,42 eV) présentent des avantages par rapport à leurs concurrents en Si et en GaAs pour les applications d’amplificateurs de puissance RF, la rectification et la commutation à forte puissance. La densité de puissance atteinte par les transistors GaN à effet de champ à haute mobilité (GaN-HEMTs) a dépassé 40 W∙mm[indice supérieur -1] à 4 GHz [Wu, Y.F. et al 2006]. Cependant, la génération de chaleur dans le canal provoque une augmentation de la température du semi-conducteur (autoéchauffement) qui provoque à la fois une diminution de la mobilité des électrons, ce qui va diminuer la performance du dispositif. Si la température du dispositif dépasse certaines limites, le dispositif risque de se dégrader de façon permanente avec un impact négatif sur la fiabilité [Nuttinck, S. et al., 2003]. Ainsi, il est très important de déterminer de façon fiable la température du canal dans les conditions réelles de fonctionnement pour modéliser le comportement des composants et pour obtenir les niveaux de performance et de fiabilité requises pour le progrès de cette technologie prometteuse. Ce projet vise au développement d’une nouvelle méthode de mesure de la température du canal des HEMTs AlGaN/GaN par contact direct avec les dispositifs, qui soit pratique et ne demande pas des systèmes sophistiqués ni dispendieux. Ainsi, on a réalisé la conception, la fabrication et la caractérisation d’une µRTD prototype potentiellement intégrable dans les dispositifs HEMT GaN. On a obtenu des capteurs qui fonctionnent de façon quasi linéaire dans une portée de températures de 25 à 275 °C et potentiellement au-delà de ces limites. On a réalisé des échantillons de transistors GaN avec des µRTDs intégrés, on a développé des dispositifs auxiliaires pour la calibration de µRTDs et pour la réalisation des mesures de température de canal (Tch) sous plusieurs conditions de polarisation. Dans un échantillon prototype, les valeurs de Tch mesurées avec le µRTD sont en accord avec des simulations 3D à éléments finis à plusieurs conditions de polarisation d’un dispositif sans-grille. Les mesures montrent des effets négligeables de perturbation électrique entre le dispositif et la µRTD [Arenas, O., et al., 2014 A]. Sur des échantillons de deuxième génération, on a mesuré la T[indice inférieur ch] d’HEMTs GaN sous plusieurs conditions de polarisation sur substrats en SiC et en saphir pour obtenir une carte Ids-Vds-Tch pour chaque dispositif [Arenas, O., et al., 2014 B]. Ainsi, les résultats obtenus démontrent que l’on peut mesurer la Tch d’un HEMT GaN polarisé en DC avec un µRTD avec peu d’interférence électrique et peu de perturbation thermique sans avoir besoin d’équipements sophistiqués ni onéreux. À l’avenir la méthode proposée peut potentiellement être appliquée sur dispositifs de plus petite taille si l’on utilise des technologies de fabrication basées sur la lithographie par faisceau d’électrons. Ainsi, elle pourra bientôt être disponible dans les plaques des dispositifs de production et de recherche.

No description available.

In this work fabrication and studies of transistor structures based on an atomic sheet of graphite, graphene, are described. Since graphene technology is in its early stages, the development and optimisation of the fabrication process are very important. In this work the impact of various fabrication conditions on the quality of graphene devices is investigated, in particular the effects on the carrier mobility of the details of the mechanical exfoliation procedure, such as environmental conditions and humidity, source of graphite and wafer cleaning procedure. In addition, a comparison is made between the conventional e-beam lithorgaphy and lithography-free fabrication of samples. It was also demonstrated that water and other environmental species play an important role in graphene-to-substrate adhesion and can also contribute to the carrier scattering in graphene. A technique for creating suspended metal gates was developed for the fabrication of graphene p-n-p structures, and charge transport has been studied in such top-gated graphene devices. Depending on the relation between the carrier mean free path and the length of the top-gate we have realized three distinct transport regimes through the p-n-p structure: a) diffusive across the structure; b) ballistic in the regions of p-n junctions but diffusive in the n-region; c) ballistic across the whole p-n-p structure. The second regime has revealed the chiral nature of carriers in graphene. This was demonstrated by comparing the experimental resistance of a single p-n junction with results of electrostatic modeling in the diffusive model. In the third regime we have observed oscillations of the device resistance as a function of carrier concentration in the n-region, which are also dependent on magnetic field. These oscillations have been demonstrated to be a direct consequence of a Fabri-Perot-like interference effect in the graphene p-n-p structures.

In dieser Arbeit wurden Einzel-Quantenpunkt-Speichertransistoren im Experiment untersucht und wesentliche Ergebnisse durch Modellierung nachgebildet. Der Einzel-Quantenpunkt-Speichertransistor ist ein Bauelement, welches durch eine neuartige Verfahrensweise im Schichtaufbau und bei der Strukturierung realisiert wurde. Hierbei sind vor allem zwei Teilschritte hervorzuheben: Zum einen wurde das Speicherelement aus positionskontrolliert gewachsenen InAs Quantenpunkten gebildet. Zum anderen wurden durch eine spezielle Trockenätztechnik schmale Ätzstrukturen erzeugt, welche sehr präzise an der lateralen Position der Quantenpunkte ausgerichtet war. Durch diese Verfahrensweise war es somit möglich, Transistorstrukturen mit einzelnen Quantenpunkten an den charakteristischen Engstellen des Kanals zu realisieren. / In this thesis single-quantum-dot memory-transistors have been studied in experiment and the experimental findings have been reproduced by modeling. The studied single-quantum-dot memory transistor is a device which has been realized by a novel process technique as regards layer composition and structuring. According to this there are two steps to be emphasized: First the memory element is based on site-controlled grown InAs quantum dots. Second, there has been used a unique dry etching technique to define narrow etched structures, which have been precisely aligned laterally with respect to the position of the quantum dots. Due to this method it was possible to realize transistor structures with single quantum dots centered in a quantum wire.

It has been verified by theoretical analysis, circuit simulation and test that two switch transistors in parallel in a simple sample and hold circuit can be achieve high speed with low error voltage due to charge injection. The wide transistor provides low RC time constant when it is closed and the narrow one ensures a low error voltage. However, tradeoff can be made in a specific application. A concise analytical expression for switch-induced error voltage on a switched capacitor is derived in this thesis. It can help designer to make the optimum decision. Experimentally, it was found that the optimum size of the wide transistor is several times wider than the narrow one. Delayed clock scheme can be used to make charge injection signal-independent in a basic integrator structure. Using two transistors with different sizes and clock duty cycles in parallel can take advantage of the fast speed of the wide transistor and the small charge injection error of the small transistor. However, the combination of the two devices, including the size and clock duty cycles, should be chosen carefully to achieve the improvement. / Graduation date: 1998

In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.

The work presented in this dissertation is focused on integrating organic transistor based circuits with planar microfluidic devices for discrete droplet handling. Discrete droplet based microfluidic systems are being increasingly investigated for lab-on-a-chip type applications. An essential component of a lab-on-a-chip system is the drive circuitry that runs the system. Conventionally, a variety of schemes have been implemented for acting as drivers for microfluidic devices. Organic transistor based circuits offer a viable and cost-effective option for serving as drivers for planar microfluidic devices. The magnitudes of voltages and the time scales involved in implementing these discrete droplet based systems are in good agreement with the values of voltages that can be reliably generated using organic transistor based circuits. Thus, the union of two cost-effective technologies with the ability to perform a wide variety of functions in a lab-on-a-chip type system would be highly desirable. A simple, planar microfluidic device with an open structure is implemented on a glass substrate. The device is optimized for reliable and repeatable performance using Cytop as the insulating dielectric. Cytop provides a highly hydrophobic surface for reversible wetting to take place on the application of electrical voltage. Various organic transistor based circuits are fabricated using Pentacene as the p-type semiconducting material and N,N'-bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN₂) as the n-type material. A top contact inverter, which is the most basic complementary metal oxide semiconductor circuit is fabricated and used as the driver for the planar microfluidic device. The output voltages generated by the inverter are used to actuate discrete water droplets over adjacent electrodes and also to perform merging of droplets, which is another basic functional operation that is performed on lab-on-a-chip type assemblies. Reliable and repeatable performance of the microfluidic device as well as the CMOS circuit is achieved. This work presents the first implementation of a discrete droplet based device driven by electrical voltages generated by an organic transistor based circuit. The physical mechanisms that are responsible for the motion of droplets have been investigated and contributions from electrowetting forces and dielectrophoretic forces have been resolved.