Global ETD Search

41	A fast rising, high current, monostable pulse generator Shaver, Fred Herbert, 1937- January 1961 (has links) No description available. Pulse generators. Transistor circuits.
42	Design of a transistor operational amplifier Ozdes, Demir, 1929 January 1963 (has links) No description available. Transistor amplifiers. Electronic circuits.
43	The Eccles-Jordan circuit using junction transistors Jones, Lincoln D. January 1956 (has links) No description available. Transistor circuits. Junction transistors.
44	Development of a common emitter equivalent circuit for the junction transistor Sakrison, David J. January 1956 (has links) No description available. Transistor circuits. Junction transistors.
45	A design procedure for transistor crystal oscillators McSpadden, William R., 1931- January 1959 (has links) No description available. Transistors. Oscillators, Transistor.
46	Temperature dependance of silicon bipolar transistor D.C. parameters Hayes, R. C. January 1986 (has links) No description available. 621.31042 Transistor design modelling
47	A study of failure locus of NPN transistors and its improvement using graded collector structures Humphreys, M. J. January 1988 (has links) No description available. 621.31042 Bipolar transistor failure
48	Clock-feedthrough compensation in MOS sample-and-hold circuits Fuchs, Franz Xaver January 2001 (has links) All MOS sample-and-hold circuits suffer to a greater or lesser extent from clock-feedthrough (CLFT), also called charge-injection. During the transition from sample to hold mode, charge is transferred from an MOS transistor switch onto the hold capacitor, thus the name charge-injection. This error can lead to considerable voltage change across the capacitor, and predicting the extent of the induced error potentials is important to circuit designers. Previous studies have shown a considerable dependency of CLFT on signal voltage, circuit impedances, clock amplitude and clock fall-time. The focus of this work was on the signal dependency of the CLFT error and on the CLFT induced signal distortion in open-loop sample-and-hold circuits. CLFT was found to have a strongly non-linear, signal dependent, component, which may cause considerable distortion of the sampled signal. The parameters influencing this distortion were established. It was discovered that distortion could be reduced by more than 20dB through careful adjustment of the clock fall-rate. Several circuit solutions that can help reduce the level of distortion arising from CLFT are presented. These circuits can also reduce the absolute level of CLFT. Simulations showed their effectiveness, which was also proven in silicon. The CLFT reduction methods used in these circuits are easily transferable to other switched-capacitor circuits and are suitable for applications where space is at a premium (as, for example, in analogue neural networks). A new saturation mode contribution to CLFT was found. It is shown to give rise to increased CLFT under high injection conditions. 621.3192 CLFT; Transistor
49	The automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University Lee, Hoon-Kyeu. January 1986 (has links) Thesis (M.S.)--Ohio University, November, 1986. / Title from PDF t.p. Logic circuits. Transistor circuits.
50	The design of power combined oscillators suitable for millimetre-wave development / Sayyah, Ali Afkari. January 1997 (has links) (PDF) Thesis (Ph. D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1997? / Includes bibliographical references (leaves 272-279.).

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