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The Ebers-Moll model, which is applicable to static or quasi-static conditions, is used as a basis for developing a simple method for the evaluation of harmonic distortion generated in bipolar transistor amplifiers. The Ebers-Moll equations are transformed into the desired forms using a Maclaurin Series expansion. A computer program is written to provide numerical results of the method, and these prediction are compared to measured distortion values.

Ce document traite de la caractérisation et la modélisation des transistors multi-ports. Une caractérisation des transistors pHEMT à base de l'AsGa est réalisée. Une importance particulière est donné aux méthodes de caractérisation RF sous pointes. En effet, une étude sur les méthodes d’épluchage est réalisée. Ensuite, après avoir relevé un défaut dans la méthode choisie (à savoir la méthode Pad-Open-Short), une solution est proposée concernant les standards non idéaux. Finalement, des modèles non linéaires 3 et 4 ports sont développés, ils ont pour objectifs de réduire le temps, des phases de conception et de fiabiliser le prototypage des fonctions micro-ondes utilisant ces composants. Les travaux présentés ici sont dédiés à l’amélioration de la modélisation électrique des transistors axée, comme leur application, sur la bande Ku. / This paper presents an approach for the de-embedding and modeling of multi-port transistors. First, the proposed de-embedding method is an extension of a three step method (Pad-Open-Short) for accurate on wafer (MMIC) S-parameters measurements. The novelty of this approach lies in the fact that the proposed de-embedding method for multi-port devices takes into account the imperfections of the standards. Then, we present two approach for the modeling of 3 and 4 ports GaAs HEMT transistors. The non-linear model was developed from I-V and S-parameters measurements. The methodology for 3-port device modeling allows us to determine accurate non-linear model in high frequencies. The second approach is dedicated for the distributed modeling of a 4-port transistor. The original electrical models of multi-port transistors developed in this thesis aims to reduce the time and the design phases, and to make reliable the prototyping of microwave functions using these components. The work presented here is therefore dedicated to improving the electrical modeling of transistors focused as their application on the Ku band.

Im Rahmen der vorliegenden Arbeit wurden Zinkoxid (ZnO)-basierte Metal-Isolator-Halbleiter Feldeffekttransistoren (MISFETs) mit Wolframtrioxid als transparentes Dielektrikum untersucht. Im ersten Teil werden die morphologischen, optischen, elektrischen und chemischen Eigenschaften der mittels gepulster Laserabscheidung (PLD) gewachsenen Wolframoxiddünnfilme, in Abhängigkeit vom Züchtungsdruck, diskutiert. Mit Hilfe dieser Ergebnisse konnte schließlich das hochisolierende Wolframtrioxid erfolgreich mit einer transparenten Gateelektrode, bestehend aus dem entarteten Halbleiter Zink-Galliumoxid (ZGO) bzw. Zink-Aluminiumoxid (AZO), kombiniert und somit MISFETs auf kristallinen und amorphen Substraten realisiert werden. Zur Optimierung der Transistoreigenschaften wurde die Dicke des Dielektrikums variiert und der Einfluss auf die Transfereigenschaften diskutiert. Des Weiteren wurde zur Verschiebung der Einschaltspannung eine Variation der Kanaldicke und des Elektrodenmaterials des Gates untersucht, wodurch die Möglichkeit der Herstellung von Verarmungs- bzw. Anreicherungstyptransistoren gegeben wurde. Um einen Vergleich der Transfereigenschaften des MISFETs gegenüber einem Metall-Halbleiter Feldeffekttransistor mit einem Schottky-Gatekontakt, bestehend aus oxidiertem Platin bzw. einem Sperrschicht-Feldeffekttransistor mit Zinkkobaltit als p-dotierten Bereich zu ermöglichen, wurden alle drei Transistorarten auf einem Substrat hergestellt und umfassend verglichen. Schließlich wird die Stabilität der Transistoren untersucht. Dabei wird der Einfluss einer permanenten Spannungsbelastung auf die Transfereigenschaften unter verschiedenen einflussnehmenden Bedingungen diskutiert. Abschließend werden aufgrund einer sich ausbildenden Hysterese der Transistoreigenschaften mögliche Ursachen derselben und Wege zur Passivierung der Bauelemente untersucht.

The fabrication processes development for on III-nitride (III-N) heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs) and metal-insulator-semiconductor field-effect transistors (MISFETs) were performed. D.c, microwave and quasi-static I-V and C-V measurements were carried out to characterize the fabricated III-N transistors and diodes. The GaN/InGaN direct-growth HBTs (DG-HBTs) grown on free-standing GaN (FS-GaN) substrates demonstrated a high current gain (hfe) > 110, high current density (JC) > 141 kA/cm2, and high power density (Pdc) > 3 MW/cm2. The first III-N DG-HBT showing fT > 8 GHz and fmax > 1.3 GHz were also demonstrated on sapphire substrates. Recessed-gate AlGaN/AlN/GaN HFETs demonstrated Vth = 0 V with 0.17 V deviation across the sample. Baliga's figure of merit is 240 MW/cm2 was achieved. Current collapse was eliminated and the dynamic on-resistance was reduced by 67% after using a remote-oxygen-plasma treatment. Normally-off recessed-gate AlGaN/AlN/GaN MISFETs with Vth = 0.9 V were also fabricated with the remote-oxygen-plasma treatment. Low leakage current (< 1 pA/mm), high on-off ratio (> 2.2E11) are achieved. These achievements suggest that high-performance III-N transistors are very promising for high-power switching and microwave amplification. Findings concerning remaining process issues and implications for future research are also discussed.

Th.--Sci. phys.--Bordeaux 1, 1978. N°: 600.

Récemment, la course à la miniaturisation a vue sa progression ralentir à cause des défis technologiques qu’elle implique. Parmi ces obstacles, on trouve l’impact croissant de la variabilité local et process émanant de la complexité croissante du processus de fabrication et de la miniaturisation, en plus de la difficulté à réduire la longueur du canal. Afin de relever ces défis, de nouvelles architectures, très différentes de celle traditionnelle (bulk), ont été proposées. Cependant ces nouvelles architectures demandent plus d’efforts pour être industrialisées. L’augmentation de la complexité et du temps de développement requièrent de plus gros investissements financier. De fait il existe un besoin réel d’améliorer le développement et l’optimisation des dispositifs. Ce travail donne quelques pistes dans le but d’atteindre ces objectifs. L’idée, pour répondre au problème, est de réduire le nombre d’essai nécessaire pour trouver le processus de fabrication optimal. Le processus optimal est celui qui conduit à un dispositif dont les performances et leur dispersion atteignent les objectifs prédéfinis. L’idée développée dans cette thèse est de combiner l’outil TCAD et les modèles compacts dans le but de construire et calibrer ce que l’on appelle un PCM (Process Compact Model). Un PCM est un modèle analytique qui établit les liens entre les paramètres process et électriques du MOSFET. Il tire à la fois les bénéfices de la TCAD (puisqu’il relie directement les paramètres process aux paramètres électriques) et du modèle compact (puisque le modèle est analytique et donc rapide à calculer). Un PCM suffisamment prédictif et robuste peut être utilisé pour optimiser les performances et la variabilité globale du transistor grâce à un algorithme d’optimisation approprié. Cette approche est différente des méthodes de développement classiques qui font largement appel à l’expertise scientifique et à des essais successifs dans le but d’améliorer le dispositif. En effet cette approche apporte un cadre mathématique déterministe et robuste au problème.Le concept a été développé, testé et appliqué aux transistors 28 et 14 nm FD-SOI ainsi qu’aux simulations TCAD. Les résultats sont exposés ainsi que les recommandations nécessaires pour implémenter la technique à échelle industrielle. Certaines perspectives et applications sont de même suggérées. / Recently, the race for miniaturization has seen its growth slow because of technological challenges it entails. These barriers include the increasing impact of the local variability and processes from the increasing complexity of the manufacturing process and miniaturization, in addition to the difficult of reducing the channel length. To address these challenges, new architectures, very different from the traditional one (bulk), have been proposed. However these new architectures require more effort to be industrialized. Increasing complexity and development time require larger financial investments. In fact there is a real need to improve the development and optimization of devices. This work gives some tips in order to achieve these goals. The idea to address the problem is to reduce the number of trials required to find the optimal manufacturing process. The optimal process is one that results in a device whose performance and dispersion reach the predefined aims. The idea developed in this thesis is to combine TCAD tool and compact models in order to build and calibrate what is called PCM (Process Compact Model). PCM is an analytical model that establishes linkages between process and electrical parameters of the MOSFET. It takes both the benefits of TCAD (since it connects directly to the process parameters electrical parameters) and compact (since the model is analytic and therefore faster to calculate). A sufficiently robust predictive and PCM can be used to optimize performance and overall variability of the transistor through an appropriate optimization algorithm. This approach is different from traditional development methods that rely heavily on scientific expertise and successive tests in order to improve the system. Indeed this approach provides a deterministic and robust mathematical framework to the problem. The concept was developed, tested and applied to transistors 28 and 14 nm FD-SOI and to TCAD simulations. The results are presented and recommendations to implement it at industrial scale are provided. Some perspectives and applications are likewise suggested.

No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

Du fait de ses propriétés intéressantes, le domaine de fréquence térahertz (THz) du spectre électromagnétique peut avoir de nombreuses applications technologiques, de l'imagerie à la spectroscopie en passant par les télécommunications. Toutefois, les contraintes technologiques empêchant l'émission et la détection efficaces de ces ondes par des systèmes conventionnels ont valu à cette partie du spectre électromagnétique le nom de gap THz. Au cours des deux dernières décennies, plusieurs solutions novatrices sont apparues. Parmi elles, l'utilisation de transistors à effet de champ s'est imposée comme une solution originale, bon marché, avec un fort potentiel d'intégration. Le mécanisme identifié fait intervenir l'interaction entre les ondes THz et des ondes de courant (dites ondes plasma) dans le canal du transistor. Le canal du transistor agit tel une cavité pour ces ondes plasma. Le dispositif peut alors se comporter de manière résonante ou non-résonante en fonction de divers paramètres. Dans ce manuscrit, nous étudions numériquement ces différents régimes à l'aide de modèles hydrodynamiques. Les modèles utilisés élargissent les phénomènes pris en compte dans de précédentes études théoriques. Les résultats portent sur la détection d'ondes THz par des transistors et dans une moindre mesure sur leur émission. Dans le régime non-résonant, nous étudions dans quelle mesure la plage de linéarité de détection peut être étendue. Dans le régime résonant, nous montrons l'existence de nouvelles fréquences de résonance, permettant d'élargir le spectre d'intérêt de ces détecteurs. / Due to its interesting properties, the electromagnetic THz frequency range may lead to numerous technological applications, ranging from imaging to spectroscopy or even communications. However, technological constraints prevented the efficient emission and detection of such waves with conventional electronics, leading to the idea of the terahertz gap. In the last decades, multiple novel solutions to resolve this gap have been proposed. Amongst these, one may find the use of simple field effect transistors as the most promising one. Their production benefits from currently available CMOS technology thus drastically decreasing the fabrication cost of such a device while allowing it to be easily integrated within electronic circuits. The mechanism behind the emission and detection is the interaction between THz electromagnetic radiations and current oscillations, that is plasma waves, in the transistor's channel. This channel forms a cavity for plasma oscillations, hence, the device may act either resonantly or non-resonantly, depending on various parameters. This thesis deals with the numerical simulation of the transistor in different regimes using hydrodynamical models. These models account for multiple phenomena that have been considered in previous theoretical studies. Some theoretical results on both the emission and detection of THz radiation are presented. In the non-resonant case, we study how one can increase the linear regime of detection. In the resonant case, we show the existence of unexpected resonance frequencies, enlarging the detection spectrum of such detectors.