O desempenho de uma linha de transmissão de energia está diretamente ligado ao número médio anual de descargas que nela incidem, o qual depende da densidade média de descargas ao solo na região e também do grau de exposição da linha. Modelos com diferentes graus de complexidade são encontrados na literatura para a estimativa da área de atração de estruturas a descargas atmosféricas. Entretanto, além das grandes simplificações sobre a física das descargas nas quais a maioria desses modelos se baseia, até recentemente não era possível considerar a configuração tridimensional das estruturas. Essa é uma limitação importante, pois detalhes do objeto afetam o campo elétrico e, consequentemente, o processo de formação do líder ascendente. Nesse contexto, o modelo desenvolvido em 2006 por Becerra e Cooray - SLIM (\"self-consistently interception model\") utiliza os conceitos mais recentes da física das descargas para a análise dos processos de formação e propagação do líder. Ao contrário dos demais modelos, o SLIM possibilita que se leve em conta a geometria tridimensional da estrutura. O modelo foi validado com base em comparações entre valores de campo elétrico para estabilização do líder em função da altura calculados e medidos em experimentos utilizando a técnica de descargas provocadas por foguetes, tendo-se obtido excelente concordância entre os resultados. Este trabalho destaca os aspectos mais importantes do SLIM e apresenta uma análise comparativa do mesmo com outros modelos bastante conhecidos, como o Modelo Eletrogeométrico, o Modelo de Eriksson e o Modelo de Rizk, além do procedimento simplificado recomendado pelo Guia IEEE Std. 1243. A análise é feita em termos da distância e do raio de atração, do número de descargas incidentes em uma linha de transmissão e do desempenho da mesma frente a descargas atmosféricas, discriminando as taxas de falhas causadas por falha de blindagem e por \"backflashover\". / In general, about 20 % to 60 % of the electric power service interruptions of distribution lines are attributed to lightning. For transmission lines, a typical figure is 70 %. The appraisal of the lightning performance of a power line is related to its mean flash collection rate, which depends on the mean ground flash density of the region and on the line exposure to direct lightning strokes. Models of different degrees of complexity are found in the literature for the estimation of lightning striking distances of objects and structures. However, besides the oversimplifications of the physical nature of the lightning discharge on which most of the models are based, till recently the tridimensional structure configuration could not be considered. This is an important limitation, as edges and other details of the object affect the electric field and, consequently, the upward leader initiation. Within this context, the self-consistently interception model (SLIM) proposed in 2006 by Becerra and Cooray is state-of-the-art leader inception and propagation leader model based on the physics of leader discharges which, unlike the other existing models, enables the tridimensional geometry of the structure to be taken into account. For the validation of the model, data obtained in rocket-triggered lightning experiments were used and an excellent agreement was found between measured and calculated leader stabilization electric fields as a function of the height of the rocket. This work describes the most important aspects of the new model and presents a comparative analysis of SLIM and other well-known model such as the Electrogeometric Model (EGM), Erikssons Model, and Rizks Model, as well as the simplified procedure recommended by IEEE Std. 1243. The analysis is done in terms of the striking distance, attractive radius, and the flash collection rate of a transmission line, as well as on its lightning performance, discriminating between the failure rates caused by shielding failure and backflashover.

Power transmission network is the most important link in the country’s energy system as they carry large amounts of power at high voltages from generators to substations. Modern power system is a complex network and requires high-speed, precise, and reliable protective system. Faults in power system are unavoidable and overhead transmission line faults are generally higher compare to other major components. They not only affect the reliability of the system but also cause widespread impact on the end users. Additionally, the complexity of protecting transmission line configurations increases with as the configurations get more complex. Therefore, prediction of faults (type and location) with high accuracy increases the operational stability and reliability of the power system and helps to avoid huge power failure. Furthermore, proper operation of the protective relays requires the correct determination of the fault type as quickly as possible (e.g., reclosing relays). With advent of smart grid, digital technology is implemented allowing deployment of sensors along the transmission lines which can collect live fault data as they contain useful information which can be used for analyzing disturbances that occur in transmission lines. In this thesis, application of machine learning algorithms for fault classification and location identification on the transmission line has been explored. They have ability to “learn” from the data without explicitly programmed and can independently adapt when exposed to new data. The work presented makes following contributions: 1) Two different architectures are proposed which adapts to any N-terminal in the transmission line. 2) The models proposed do not require large dataset or high sampling frequency. Additionally, they can be trained quickly and generalize well to the problem. 3) The first architecture is based off decision trees for its simplicity, easy visualization which have not been used earlier. Fault location method uses traveling wave-based approach for location of faults. The method is tested with performance better than expected accuracy and fault location error is less than ±1%. 4) The second architecture uses single support vector machine to classify ten types of shunt faults and Regression model for fault location which eliminates manual work. The architecture was tested on real data and has proven to be better than first architecture. The regression model has fault location error less than ±1% for both three and two terminals. 5) Both the architectures are tested on real fault data which gives a substantial evidence of its application.

A true time delay multi-bit MEMS phase shifter topology based on impedance-matched slow-wave CPW sections on a 500µm thick quartz substrate is presented. Design equations based on the approximate model for a distributed line is derived and used in optimization of the unit cell parameters. A semi-lumped model for the unit cell is derived and its equivalent circuit parameters are extracted from measurement and EM simulation data. This unit cell model can be cascaded to accurately predict N-section phase shifter performance. Experimental data for a 4.6mm long 4-bit device shows a maximum phase error of 5.5° and S11 less than -21dB from 1-50GHz. A reconfigurable MEMS transmission line based on cascaded capacitors and slow-wave sections has been developed to provide independent Zo - and β-tuning. In the Zo-mode of operation, a 7.4mm long line provides Zo-tuning from 52 to 40Ω (+/-2Ω) with constant phase between the states through 50GHz. The same transmission line is reconfigured by addressing the MEM elements differently and experimental data for a 1-bit version shows 358°/dB (or 58°/mm) with S11 less than -25dB at 50GHz. The combined effect of Zo- and β-tuning is also realized using a 5-bit version. An electronically tunable TRL calibration set that utilizes a 4-bit true time delay MEMS phase shifter topology, is demonstrated. The accuracy of the tunable TRL is close to a conventional multi-line TRL calibration and shows a maximum error bound of 0.12 at 40GHz. The Tunable TRL method provides for an efficient usage of wafer area while retaining the accuracy associated with the TRL technique, and reduces the number of probe placements.

Abstract not available

Nowadays power transmission networks are capable of delivering contracted power from any supplier to any consumer over a large geographic area under market control, and thus transmission lines are incorporated with FACTs series compensated devices to increase the power transfer capability with improvement to system integrity. Conventional fault location methods developed in the past many years are not suitable for FACTs transmission networks. The obvious reason is that FACTs devices in transmission networks introduce non-linearity in the system and hence linear fault detection methods are no longer valid. Therefore, it is still a matter of research to investigate developing new fault detection techniques to cater for modern transmission network configurations and solve implementation issues maintaining required accuracy. This PhD research work is based on developing an accurate and robust new fault location algorithm for series compensated high voltage transmission lines, considering many issues such as transmission line models, configurations with series compensation features. Building on the existing knowledge, a new algorithm has been developed for the estimation of fault location using the time domain approach. In this algorithm, instantaneous fault signals from the transmission line ends are measured and applied to the algorithm to calculate the distance to fault. The new algorithm was tested on two port transmission line model developed using EMTP/ATP software and measured fault data from the simulations are exported to the MATLAB space to run the algorithm. Broad range of faults has been simulated considering various fault cases to test the algorithm and statistical results obtained. It was observed that the accuracy of location of fault on series compensated transmission line using this algorithm is in the range from 99.7 % to 99.9% in 90% of fault cases. In addition, this algorithm was further improved considering many practical issues related to modern series compensated transmission lines (with TCSC var compensators) achieving similar accuracies in the estimation of fault location.

<p>The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. In fact, global interconnects extending across a full chip can have a delay corresponding to multiple clock cycles. At the same time, global clock skew constraints, not only between blocks but also along the pipelined interconnects, become even tighter. On-chip interconnects have always been considered <em>RC</em>-like, that is exhibiting long <em>RC</em>-delays. This has motivated large efforts on alternatives such as on-chip optical interconnects, which have not yet been demonstrated, or complex schemes utilizing on-chip F-transmission or pulsed current-mode signaling.</p><p>In this thesis, we show that well-designed electrical global interconnects, behaving as transmission lines, have the capacity of very high data rates (higher than can be delivered by the actual process) and support near velocity-of-light delay for single-ended voltage-mode signaling, thus mitigating the <em>RC</em>-problem. We critically explore key interconnect performance measures such as data delay, maximum data rate, crosstalk, edge rates and power dissipation. To experimentally demonstrate the feasibility and superior properties of on-chip transmission line interconnects, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over the 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 μm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.</p><p>To manage the problems due to global wire delays, we describe and implement a Synchronous Latency Insensitive Design (SLID) scheme, based on source-synchronous data transfer between blocks and data re-timing at the receiving block. The SLIDtechnique not onlymitigates unknown globalwire delays, but also removes the need for controlling global clock skew. The high-performance and high robustness capability of the SLID-method is practically demonstrated through a successful implementation of a SLID-based, 5.4 mm long, on-chip global bus, supporting 3 Gb/s/wire and dynamically accepting ± 2 clock cycles of data-clock skew, in a standard 0.18 μm CMOS porcess.</p><p>In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition-energy cost model aimed for efficient power estimation of performancecritical buses. The model, which includes properties that closely capture effects present in high-performance VLSI buses, can be used to more accurately determine the energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a microprocessor cache bus architecture used in industry.</p>

In this thesis the network analog method is used to analyze various planar multi-conductor structures in multilayered, lossy dielectric media. The method is based on an efficient impedance network representation of the finite difference approximation of Laplace's equation for the electric potential. Using the network analog method, the transmission line parameters are computed for several different uniform stripline structures in lossless and lossy multilayered dielectric material. The network analog method is also applied to several three-dimensional structures consisting of single and coupled conducting patches of rectangular shape. Results obtained with the network analog method for single conducting patches in single and multilayered lossless dielectric media are in good agreement with published results based on a variational approach. Further results presented in this thesis include the coupling capacitance for coplanar and multilevel patch configurations in lossless and lossy multilayered dielectric media. / Graduation date: 2000

The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. In fact, global interconnects extending across a full chip can have a delay corresponding to multiple clock cycles. At the same time, global clock skew constraints, not only between blocks but also along the pipelined interconnects, become even tighter. On-chip interconnects have always been considered RC-like, that is exhibiting long RC-delays. This has motivated large efforts on alternatives such as on-chip optical interconnects, which have not yet been demonstrated, or complex schemes utilizing on-chip F-transmission or pulsed current-mode signaling. In this thesis, we show that well-designed electrical global interconnects, behaving as transmission lines, have the capacity of very high data rates (higher than can be delivered by the actual process) and support near velocity-of-light delay for single-ended voltage-mode signaling, thus mitigating the RC-problem. We critically explore key interconnect performance measures such as data delay, maximum data rate, crosstalk, edge rates and power dissipation. To experimentally demonstrate the feasibility and superior properties of on-chip transmission line interconnects, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over the 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 μm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum. To manage the problems due to global wire delays, we describe and implement a Synchronous Latency Insensitive Design (SLID) scheme, based on source-synchronous data transfer between blocks and data re-timing at the receiving block. The SLIDtechnique not onlymitigates unknown globalwire delays, but also removes the need for controlling global clock skew. The high-performance and high robustness capability of the SLID-method is practically demonstrated through a successful implementation of a SLID-based, 5.4 mm long, on-chip global bus, supporting 3 Gb/s/wire and dynamically accepting ± 2 clock cycles of data-clock skew, in a standard 0.18 μm CMOS porcess. In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition-energy cost model aimed for efficient power estimation of performancecritical buses. The model, which includes properties that closely capture effects present in high-performance VLSI buses, can be used to more accurately determine the energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a microprocessor cache bus architecture used in industry.

This thesis explores and implements techniques for frequency domain modelling and time domain simulation of overhead transmission lines. The popular Vector Fitting algorithm is employed to approximate the frequency domain model using rational functions, and the recursive convolution technique is applied to the rational approximation to generate a time domain form. The frequency domain model is translated into the time domain using delay extraction, modal decomposition, passivity enforcement, and rational approximation. Several approaches to each of these procedures are investigated. The thesis also discusses several choices for the integration method used within the recursive convolution procedure. In order to make the transmission line modeller and simulator easy to use, a Java-based library and partial graphical interface were developed. Specifically, the goal was to develop a platform-independent program that can run either stand-alone or as an applet inside a web page. / October 2005

Long resistive cables used in the operation of remote instrumentation impose fundamental limits on the amount of power delivered and create difficulties in voltage regulation at the remote-end (voltage at the end of the cable) with changing load conditions. This type of power delivery is used in many engineering systems such as in the operation of underwater remotely-operated vehicles, in oil drilling and mining industries, and in highly distributed systems (aircraft, submarines, and space stations, etc.). The focus of this research is to develop new approaches for power delivery in systems that have considerable voltage drops between the local and remote-ends.Two novel methods of power delivery based on state feedback control and parallel operation of switching and linear regulators to enhance stability and increase the power delivered at the remote-end are developed and validated experimentally.A system-level approach is developed to control the remote-end voltage for changing load conditions through the usage of a model inversion technique at the local-end along with a feedback of the local-end variables.