The thesis deals with the implementation of Ethernet-based network communication interface into FPGA chip. VHDL programming language is used for description of the hardware. The interface includes the implementation of link-layer Ethernet protocol and network protocols such as IPv4, ARP, ICMP and UDP. The final design allows bi-directional communication on the transport-layer level of TCP/IP model. The designed interface was implemented into Virtex5 FPGA chip on development board ML506 by Xilinx.

Práce uvádí základní informace o průmyslové sběrnici AS-Interface a popisuje její funkce. Dále se zabývá rozšířením stávajícího FTZ AS-Interface Slave Simulátoru o dotykový display, který značně usnadní ovládání tohoto simulačního nástroje. Je zde nastíněn návrh a řešení uživatelského dotykového rozhraní k tomuto simulátoru s použitím Amulet LCD modulu STK 480272C. Vývoj tohoto rozhraní je proveden pomocí GEMstudia, softwaru firmy Amulet Technologies a grafických programů. Dále tato studie pojednává o softwarové úpravě FTZ AS-i Slave Smilulátoru. Jedná se o úpravu řídícího FPGA v jazyce VHDL zajišťující komunikaci s dotykovým displejem. Poslední kapitola se týká problematiky spojené s návrhem uživatelsky přívětivé aplikace.

Goal of this doctoral thesis is to focus to understand of behavior of working of basic electronics circuits and to appoint which parameters of these circuits is possible to control using external digital system. Further the examples of some digitally controlled analog circuits are present and the analysis of these circuits is achieved. Some of these blocks are realized and the results of that’s measuring is presented.

The dissertation deals with simulations of the DC-DC converters in their basic configurations (Buck, Boost, Buck-boost, Cuk, SEPIC). In the first part of the thesis derivation of transfer functions Line-to-Output (LTO) and Control-To-Output (CTO) can be found. These symbolic responses are derived for three types of basic converters (Buck, Boost, Buck-boost) using well-known average model [1]. Derived expressions are very complicated. For reduction of these expressions symbolic approximation method was used, however the generality is lost. The average model was used to for decreasing the computational effort of analysis of DC-DC converters in the time domain. For these simulations VHDL-AMS language was used. The main topic of the thesis is harmonic balance method, which was adapted to DC-DC converters. Because conditions and assumptions for LTO and CTO functions are very different, harmonic balance method was derived into two variants. For obtaining of LTO response, duty cycle of switching signal can be considered as constant in time. Spectrum of this signal is simple as follows from well-known sinc function. For obtaining of CTO response PWM modulation must be used. Compared to sinc function spectrum of PWM modulation is richer (contains more combination frequencies). Many types of PWM modulation is described in [31]. For simulation PWM modulation with uniform sampling in two variants (single and double edge) was used. Non-ideal switching of PWM switch was modeled by PWM pulse with defined slew rate. Last section deals with comparison of all derived functions (LTO, CTO, modulation type, defined slew rate) with well-known averaged model.

The aim of this thesis is to research how the functional paradigm can be used for hardware acceleration with an emphasis on data-parallel tasks. The level of abstraction of the traditional hardware description languages, such as VHDL or Verilog, is becoming to low. High-level languages from the domains of software development and modeling, such as C/C++, SystemC or MATLAB, are experiencing a boom for hardware description on the algorithmic or behavioral level. Functional Languages are not so commonly used, but they outperform imperative languages in verification, the ability to capture inherent paralellism and the compactness of code. Data-parallel task are often accelerated on FPGAs, GPUs and multicore processors. In this thesis, we use a library for general-purpose GPU programs called Accelerate and extend it to produce VHDL. Accelerate is a domain-specific language embedded into Haskell with a backend for the NVIDIA CUDA platform. We use the language and its frontend, and create a new backend for high-level synthesis of circuits in VHDL.

This project deals with computation of eigenvalues and eigenvectors of Hermitian positive-semidefinite complex square matrix of order 4. The target is an implementation of computation in language VHDL to field-programmable gate array of type Xilinx Zynq-7000. This master project deals with algorithms used for computation of eigenvalues and eigenvectors of positive-semidefinite symmetric real square and positive-semidefinite complex Hermitian matrix and the analysis of algorithms by AnalyzeAlgorithm program assembled for this purpose. The closing part of this project describes implementation of the computation into field-programmable gate array with use of IP core Xilinx® Floating-Point \linebreak Operator and SVAOptimalizer, SVAInterpreter and SVAToDSPCompiler programs.

No description available.

Due to growing transmission speed burst-forming errors tend to occur still more frequently not exclusively in data transmission. The presented paper concentrates on the search for alternative burst error correction solutions complementing the existing methods in use. Its objective is an elaboration of a detailed analysis of the issue of convolution codes for error burst correction which can be used in individual anti-error systems and thus an achievement of better results than those attained by mass application of the existing solutions. First the methods implemented to remove or suppress burst errors are briefly characterized. This part is followed by a detailed description of the individual systematic convolution codes by means of mathematical tools which extend the set of possible evaluative criteria of anti-error systems which can be applied while assessing proposals for individual solutions. The acquired code properties are compared with convolution codes as well as with other versions of proposals for message protection against an error burst. The processed convolution codes are subject to testing by means of Matlab mathematical programme simulation in order to validate the correctness of the derived mathematical tools. This is because simulation represents the principal method applied to verify and present an already proposed security process and enables the acquisition of a better overview of the issue at hand. The feasibility of the individual anti-error systems is then confirmed by way of creating a circuit behaviour description in the VHDL language. Its high portability presents a big advantage when drafting individual systems of the actual implementation.

This thesis deals with the design of a device that enables to monitor the behavior of the measured signal on the computer screen, using the principle of the digital oscilloscope. The control element of the device is the field programmable gate array (FPGA) on FITkit platform.  The FPGA configuration controls the input signal sampling and sends the received samples through the USB interface to the PC. The graphical application implemented in the computer tries to restore the signal and then displays it on the screen.

This paper describes various approaches to hardware testing semiconductor memory. We describe the priciple of basic memory types, the way which each of them stores information and their comunication protocol. Following part deals with common failures which may occur in the memory.  The section also describes the implementation of memory model and tester designed in VHDL language. It is possible to inject some errors into memory, which are later detected by the tester. The final section shows the response of tester to various error types according to used error detection method. The paper is especially focused on failure detection by variants of march test.