<p>This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.</p>

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18<i>&mu;</i>m CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.

This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer &amp; Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18<i>&mu;</i>m CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.

Nous proposons un modèle compact du transistor MOS double-grille silicium sur isolant (SOI) en mode de fonctionnement symétrique. Le modèle est basé sur le formalisme EKV et offre les caractéristiques suivantes : une expression analytique simple décrivant le comportement statique et dynamique du dispositif, des relations « directes » entre charges–tensions et tensions–courant, une méthode de calcul numérique robuste et rapide, une implémentation aisée du modèle dans un langage de haut niveau tel que VHDL-AMS permettant ainsi une simulation rapide et précise des caractéristiques électriques.<br />Le modèle prend en compte non seulement les effets de petites géométries tels que l'abaissement de la barrière de potentiel induit par le drain, le partage de charge, la dégradation de la pente sous le seuil ainsi que la réduction de la mobilité des porteurs, mais également les effets dynamiques extrinsèques.<br />Il a été validé pour des dispositifs de longueur de canal de 60nm. Sa validation a été effectuée par comparaison de ses résultats avec ceux obtenus sur le simulateur de composants Atlas/SILVACO.

Les réseaux de capteurs communiquant sans fil offrent des possibilités extrêmement intéressantes pour l'application de surveillance de santé de structures, et particulièrement dans le secteur aéronautique. Cependant les capteurs qui constituent chaque noeud du réseau ne disposent pas de ressources énergétiques permanentes et leur autonomie énergétique sur de longues périodes est un problème. Avec la réduction de la consommation des composants électroniques et des capteurs, une solution possible et explorée depuis une dizaine d'années par nombreuses équipes consiste à récupérer l'énergie disponible dans son environnement, de la stocker et la gérer pour alimenter le capteur. Nous proposons dans cette thèse d'exploiter le potentiel énergétique des vibrations mécaniques d'une structure aéronautique pour alimenter un capteur de surveillance de santé de structure aéronautique. Notre contribution porte sur la conception et l'intégration sur silicium d'un générateur piézoélectrique miniature et d'un micro dispositif de stockage capacitif. Concernant le générateur piézoélectrique, l'élaboration d'un modèle à éléments finis (COMSOL) couplées avec une description SPICE du circuit de charge, a permis de concevoir - une structure optimisée consistant en 4 poutres monomorphes (Si/PZT) capable de générer des puissance électrique > ?W et des tension > V en dépit de puissance mécaniques incidentes faibles : vibrations de 0,1g-0,5g @40-80 Hz. Ce dispositif a ensuite été réalisé sur silicium à l'aide de technologies MEMS et de l'usinage laser femtoseconde. Le dispositif de stockage conçu et intégré sur silicium est un condensateur à double couche électrochimique. Les différentes briques technologiques développées concernent l'optimisation des géométries d'électrodes, le dépôt de la matière active et l'encapsulation hermétique de l'électrolyte organique en atmosphère anhydre. Un modèle VHDL-AMS des deux éléments (récupérateur et stockage) réalisés est proposé et une simulation du systè me sur un cas d'utilisation simple est comparée à l'expérience.

This thesis is focused on the compression algorithm's analysis of MJPEG format and its implementation in FPGA chip. Three additional video bitstream reduction methods have been evaluated for real-time low latency applications of MJPEG format. These methods are noise filtering, inter-frame encoding and lowering video's quality. Based on this analysis, a MJPEG codec has been designed for implementation into FPGA chip XC6SLX45, from Spartan-6 family.

La réglementation mondiale, pour des appareils de courte portée, permet l’utilisation sans licence de plusieurs Gigahertz de bande autour de 60 GHz. La bande des 60 GHz répond aux besoins des applications telles que les réseaux de capteurs très haut débit autonome en énergie,ou les transmissions à plusieurs Gbit/s avec des contraintes de consommation d’énergie. Il y a encore peu de temps, les interfaces radios fonctionnant dans la bande millimétrique n’étaient réalisables qu’en utilisant des technologies III-V couteuses. Aujourd’hui, les avancées des technologies CMOS nanométriques permettent la conception et la production en masse des circuits intégrées radiofréquences (RFIC) à faible coût.Cette thèse s’inscrit dans des travaux de recherches dédiés à la réalisation d’un système dans un boîtier (SiP, System in Package) à 60 GHz contenant à la fois l’interface radio (bande de base et circuits RF) ainsi qu’un réseau d’antennes. La première partie de cette thèse est dédiée la conception de la tête RF de l’émetteur-récepteur à faible consommation pour l’interface radio. Les blocs clefs de cette tête RF (amplificateurs, mélangeurs et un oscillateur commandé en tension) sont conçus, réalisés et mesurés en utilisant la technologie CMOS 65 nm de ST Microelectronics. Des éléments actifs et passifs sont développés spécifiquement pour l’utilisation au sein de ces blocs. Une étape importante vers l’intégration de la tête RF complète de l’émetteur-récepteur est l’assemblage de ces blocs de base afin de réaliser une puce émetteur et une puce récepteur. A ce but, une tête RF pour le récepteur a été réalisée. Ce circuit présent une consommation et un encombrement plus réduit que l’état de l’art.La deuxième partie de cette thèse présente le développement des modèles comportementaux des blocs de base conçus. Ces modèles au niveau système sont nécessaires afin de simuler le comportement du SIP, qui devient trop complexe si des modèles détaillés du niveau circuitsont utilisés. Dans cette thèse, une nouvelle technique modélisant le comportement en régime transitoire et régime permanent ainsi que le bruit de phase des oscillateurs commandés en tension est proposée. Ce modèle est implémenté dans le langage de description de matérielVHDL-AMS. La technique proposée utilise des réseaux de neurones artificiels pour approximer la caractéristique non linéaire du circuit. La dynamique est décrite dans l’espace d’état. Grâce à ce modèle, il est possible de réduire d’une façon drastique le temps de calcul des simulations système tout en conservant une excellente précision / Worldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs)at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form basic transmitter and receiver chips. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished.The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemented. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy

Resumo: Atualmente, as redes de transdutores inteligentes desempenham um papel de importância vital em sistemas de Medição e Controle Distribuído. Nesse contexto, o Padrão IEEE 1451 para interfaceamento de transdutores inteligentes tem como objetivo simplificar a conectividade de transdutores em ambientes de rede, fornecendo, para tal fim, um conjunto de interfaces padronizadas, aumentando a flexibilidade dos sistemas de instrumentação distribuída. Neste trabalho descreve-se a implementação de um nó de rede em conformidade com o padrão IEEE 1451. O nó foi completamente desenvolvido através do emprego de ferramentas padronizadas e sistemas abertos. O nó é composto por um Processador de Aplicação com Capacidade de Operar em Rede (NCAP), com base no padrão IEEE 1451.1 e um Módulo de Interface para Transdutores Inteligentes (STIM), em conformidade com o padrão IEEE 1451.2. A parte física do NCAP foi implementada através dos recursos de um Computador Pessoal (PC) e de um Dispositivo Lógico Programável (PLD) de uso geral. A parte lógica do NCAP foi desenvolvida através da tecnologia Java. O STIM foi implementado com dispositivos lógicos programáveis versáteis, de uso geral, e sua funcionalidade foi integralmente descrita em linguagem de descrição de hardware. O conjunto NCAP-STIM foi conectado a uma rede de área local, sob o modelo de comunicação cliente-servidor, sendo que várias aplicações clientes podem acessar as informações dos transdutores conectados ao STIM, através da rede, via intermediação do NCAP. O emprego de ferramentas padronizadas e abertas no desenvolvimento total do sistema IEEE 1451 é uma das contribuições mais importantes do presente trabalho. No entanto, há várias contribuições pontuais como: a maneira de descrever as Informações de Transdutores em Formato Eletrônico (TEDS), a implementação... (Resumo completo, clicar acesso eletrônico abaixo). / Abstract: Nowadays, smart transducer networks play an essential role in distributed measurement and control systems. In this context, the IEEE 1451 smart transducer interface standards aimed to simplify transducer connectivity, providing a set of common interfaces for connecting transducers in a networked fashion, increasing the flexibility of distributed instrumentation systems. In this work the implementation of a network node according to the IEEE 1451 standard is introduced. The node has been fully developed using open and standardized tools. A Network Capable Application Processor (NCAP) according to the IEEE 1451.1 Standard and a Smart Transducer Interface Module (STIM) comprises the node. The physical part of the NCAP has been implemented using the resources of a Personal Computer (PC) and a general-purpose Programmable Logic Device (PLD). The logical part of the NCAP has been developed using Java technology. The STIM module was implemented with versatile, general-purpose Programmable Logic Devices. STIM functionality has been fully developed in hardware description language. A network node (STIM-NCAP) was connected in a client-server modelbased local area network. Many client applications can access STIM transducers information, through the network with the NCAP as an intermediary. One of the most important contributions of this work is the employment of open and standardized tools for implementing the IEEE 1451 network node. However, there are many specific contributions such as: Transducer Electronic Data Sheet (TEDS's) description method, programmable logic-based Protocol Manager implementation that allows the use of the parallel port without any modification, the employment of low-cost PLDs for implementing the STIM and the Protocol Manager, and Java-based NCAP software development. Through the implementation of the IEEE Standard, industries... (Complete abstract, click electronic address below). / Orientador: Aparecido Augusto de Carvalho / Coorientador: Alexandre César Rodrigues da Silva / Banca: Onofre Trindade Júnior / Banca: Edward David Moreno Ordonez / Banca: Cláudio Kitano / Banca: Ricardo Tokio Higuti / Doutor

The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.