Cette thèse aborde les formalismes pour la modélisation multi-physique en support au cycle en V de conception. Ce travail a été réalisé dans le cadre du projet ANR-MoCoSyMec, selon la méthodologie du prototypage virtuel fonctionnel (PVF) et illustré sur des systèmes électromagnétiques. Nous nous sommes principalement intéressés au langage VHDL-AMS, en tant que support aux différents niveaux de modélisation apparaissant dans le cycle en V de conception. Cela nous a conduits à traiter la portabilité et l'interopérabilité en VHDL-AMS de diverses méthodes et outils de modélisation. Nous avons proposé et validé, via le formalisme des composants logiciels ICAr, des solutions aux limites de l'utilisation de VHDL-AMS pour modéliser certains phénomènes physiques reposants sur des calculs numériques. Nous avons étendu la norme ICAr pour supporter des modèles dynamiques décrits par des équations différentielles algébriques (DAE) ; et pour des besoins de co-simulation, nous pouvons également y associer un solveur. Ces développements sont désormais capitalisés dans le framework CADES. Enfin, nous avons proposé une architecture pour le portage de modèles d'un formalisme à un autre. Elle a été définie et mise en oeuvre plus particulièrement pour des modèles magnétiques réluctants (Reluctool) et des MEMS magnétiques (MacMMems) vers le VHDL-AMS. Ces formalismes et méthodologies sont mis en oeuvre autour du PVF d'un contacteur électromagnétique.

The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation. This thesis presents the design and implementation of a modulator for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in VHDL and is intended for implementation on an FPGA.

This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm. The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF). The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project. A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa. When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s. The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.

Reproduction de : Thèse de doctorat : Informatique : Lille 1 : 2004. / Titre provenant de la page de titre du document numérisé. Bibliogr. p. 183-194.

Une nouvelle méthodologie d'extraction de modèles thermiques compacts (CTMs) pour les composants électroniques est proposée dans cette thèse. L'originalité de cette méthodologie réside dans la prise en compte du comportement thermique des composants comportant plusieurs puces ou sources de chaleur, plusieurs surfaces de refroidissement et des matériaux à propriétés non-linéaires, tout en gardant une structure simple et récurrente des modèles générés. Cette méthodologie concerne aussi les modèles thermiques dynamiques, ceci est rendu possible par l'utilisation d'un réseau simple de type " étoile ". La précision du réseau en étoile est améliorée en utilisant des résistances variables liées aux flux thermiques afin que le modèle compact puisse s'adapter à toutes les conditions aux limites possibles. De plus, la méthode choisie permet d'obtenir ceci avec un nombre limité de mesures ou de simulations thermiques 3D. Par ailleurs, tout au long du travail effectué, nous avons choisi de maintenir le lien avec la physique de façon à pouvoir toujours faire les analyses et les interprétations des phénomènes mis en jeu. Ainsi, une étude basée sur les phénomènes de répartition 3D du flux thermique a abouti à des solutions argumentées et validées pour rendre les modèles générés plus précis. L'extension des modèles thermiques compacts au régime dynamique, rendue possible par la méthodologie choisie, est proposée par le biais de trois techniques différentes. L'ajout d'un modèle électrique compatible avec les modèles thermiques développés, rendra aisée la modélisation électrothermique.

Grâce à l'augmentation continue des performances des circuits intégrés, l'électronique s'est largement développée dans la plupart des secteurs d'activité et tout particulièrement dans les systèmes embarqués. Ces systèmes doivent répondre à des contraintes de fiabilité sévères pour résister à des agressions issues de phénomènes transitoires variés, comme les décharges électrostatiques (ESD). À l'heure actuelle, l'impact de ces agressions sur le taux de retours clients des circuits intégrés est de 40 à 50 %. Pour améliorer l'immunité du système, et réduire ainsi les coûts de production et de suivi des produits, il devient nécessaire de prendre en compte ces perturbations dès la conception et d'avoir une approche globale de protection. Dans le cadre de ces travaux de thèse, nous avons développé une méthodologie de simulation, des modèles et les techniques de caractérisation associées afin d'évaluer l'impact d'un stress ESD en tous points d'une carte électronique en fonction des caractéristiques de chaque composant et du placement/routage. L'approche de modèlisation choisie s'appuie sur les outils informatiques de conception fonctionnelle des circuits et cartes et utilise le langage VHDL-AMS dont la certification IEEE en fait un standard industriel. Pour la caractérisation, l'originalité concerne l'utilisation d'un banc de test en impulsions de type Very Fast-TLP, couplé à différentes méthodes d'injection, qui permet à la fois, l'extraction des paramètres pour les modèles et d'observer la réponse du circuit intégré agressé sur la carte. Le résultat majeur de cette étude est la possibilité de simuler la réponse d'une carte électronique à une agression ESD (ex : ESD de type IEC) depuis son impact jusqu'au niveau de toute entrée/sortie des composants de la carte. L'approche est validée sur un circuit test simple mais aussi sur une application plus complexe à base d'un microcontrôleur. Elle permet de s'assurer que chaque composant est adéquat en termes de robustesse et de détecter des couplages indésirés.

Στο πρώτο μέρος της παρούσας Διπλωματικής Εργασίας εισάγονται οι βασικές έννοιες της Θεωρίας Κωδικοποίησης και των Τηλεπικοινωνιακών Συστημάτων. Για τη διόρθωση λαθών στην περίπτωση της μετάδοσης μέσω ενός θορυβώδους καναλιού εφαρμόζεται κωδικοποίηση καναλιού με Γραμμικούς Μπλοκ Κώδικες, και πιο συγκεκριμένα Κώδικες Χαμηλής Πυκνότητας Ελέγχου Ισοτιμίας (Low-Density Parity-Check Codes, LDPC). Ορίζεται η μαθηματική περιγραφή των κωδίκων αυτών και διατυπώνονται σχετικοί ορισμοί και θεωρήματα. Επίσης, διατυπώνεται το κριτήριο Μέγιστης Πιθανοφάνειας, στο οποίο βασίζεται η ανάπτυξη του αντίστοιχου αποκωδικοποιητή. Το δεύτερο μέρος περιλαμβάνει την εξομοίωση του αποκωδικοποιητή Μέγιστης Πιθανοφάνειας στο λογισμικό και την υλοποίησή του σε FPGA, στις περιπτώσεις όπου χρησιμοποιούνται Soft ή Hard είσοδοι στον αποκωδικοποιητή. Ακόμη, παρουσιάζεται η Αρχιτεκτονική του αποκωδικοποιητή και η Μεθοδολογία Σχεδίασής του. Παρουσιάζονται βελτιώσεις στη σχεδίαση του αποκωδικοποιητή που οδηγούν σε μείωση της απαιτούμενης επιφάνειας στο υλικό. Τα αποτελέσματα που προκύπτουν από τις μετρήσεις των δύο υλοποιήσεων συγκρίνονται με την περίπτωση αποκωδικοποιητή βασισμένο σε επαναλήψεις και εξάγονται τα διαγράμματα ρυθμού σφαλμάτων bit και τα αντίστοιχα συμπεράσματα. / In the first part of this thesis, the basic principles of Coding Theory and Communication Systems are introduced. In order to correct errors in the case of transmission through a noisy channel, channel coding with Linear Block Codes is applied, and more specifically Low-Density Parity-Check (LDPC) codes. The mathematical description of such codes is defined and useful definitions and theorems are specified. In addition, the Maximum Likelihood (ML) criterion is specified, on which the development of the relevant decoder is based. The second part consists of the simulation of the ML decoder in software and its hardware implementation on FPGA, in the cases where either Soft or Hard information is used as the decoder's input. Furthermore, the decoder's Architecture and the Design Methodology used are presented. Improvements concerning the implementation of the decoder are introduced, which lead to a reduction in the required area on chip. The experimental results of the two implementations are compared to the case of the iterative decoder and the Bit Error Rate plots are produced, as well as the appropriate conclusions.

Made available in DSpace on 2014-06-11T19:30:50Z (GMT). No. of bitstreams: 0 Previous issue date: 2008-12-15Bitstream added on 2014-06-13T19:40:17Z : No. of bitstreams: 1 soares_jo_dr_ilha.pdf: 2703269 bytes, checksum: f51d4821a6cb2c9c52cf4d25420d0c39 (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / O objetivo deste trabalho é a concepção de uma lógica de controle digital com modulação por histerese variável usando um dispositivo programável FPGA (Field Programmable Gate Array) e linguagem de descrição de hardware VHDL (Hardware Description Language), aplicada em um retificador trifásico híbrido para a obtenção do Fator de Potência (FP) de entrada quase unitário. O Retificador Trifásico Híbrido (RTH) é uma estrutura composta por um retificador a diodos de 6 pulsos e por três retificadores monofásicos SEPIC conectados em paralelo. O controle digital proposto é capaz de impor a forma de onda das correntes de entrada, obtendose Distorção Harmônica Total (DHT) reduzida e fator de potência (FP) quase unitário, sendo que nesta condição, os retificadores monofásicos SEPIC conduzirão no máximo 33% da potência ativa total. Além disso, o uso de FPGAs dará ao Retificador Híbrido Trifásico uma flexibilidade adicional na operação, podendo substituir vários sistemas de múltiplos pulsos convencionais e reduzir custos para o sistema de controle por eliminar a confecção de circuitos complexos de controle analógico, para os conversores chaveados. Neste trabalho, apresenta-se uma análise detalhada e metodologia de projeto para o Retificador Híbrido Trifásico (RTH) que possibilita relacionar o valor da DHT das correntes de entrada com os valores das potências média e aparente processadas pelas estruturas controlada e não-controlada, podendo-se prever o desempenho global do sistema. Serão apresentados detalhes sobre o funcionamento do código VHDL e da modulação por histerese variável empregada e, por fim, os resultados experimentais de um protótipo implementado para 3,0 kW. O código VHDL desenvolvido, associado à lógica de controle digital proposta, foi implementado através de um dispositivo FPGA da Xilinx – Spartan XC2S200E, módulo digilab-D2E... / The objective of this work is the development of a digital control logic with variable hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier in order to obtain an almost unitary input power factor (PF). The hybrid three-phase rectifier is a structure composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The proposed digital control is capable to impose input current waveforms, resulting in a reduced THD (Total Harmonic Distortion) and almost unitary input power factor, being that in this operation condition the parallel SEPIC single-phase rectifiers will process only 33.0 % of total active power. Moreover, the use of FPGA will provide to hybrid three-phase rectifier an additional flexbility in its operation, making possible the replacement of same conventional systems of multiple pulses and reducing costs for the control system, through the elimination of complex analogical circuitry used in the controlled converters. In this work is presented a detailed analysis and design methodology to hybrid threephase rectifier that establishes a relationship between the THD imposed to line input currents, with the average and apparent powers processed through controlled and uncontrolled structures, making possible to know previously the global system performance. It will be presented details about the operation of the VHDL code and variable hysteresis modulation proposed, and finally the experimental results from an implemented 3.0 kW prototype. The developed VHDL code, considering the proposed digital control logic, was implemented through a Xilinx’s FPGA device – Spartan XC2S200E, digilab-D2E module, whose generated control signals resulted in input currents with practically sinusoidal waveforms... (Complete abstract click electronic access below)

Esta dissertação de mestrado propõe uma hierarquia de memória para a Estimação de Movimento e de Disparidade (ME/DE) centrada nas referências da codificação, estratégia chamada de Reference-Centered Data Reuse (RCDR), com foco em redução de energia em codificadores de vídeo multivistas (MVC - Multiview Video Coding). Nos codificadores MVC, a ME/DE é responsável por praticamente 98% do consumo total de energia. Além disso, até 90% desta energia está relacionada com a memória do codificador: (a) acessos à memória externa para a busca das referências da ME/DE (45%) e (b) memória interna (cache) para manter armazenadas as amostras da área de busca e enviá-las para serem processadas pela ME/DE (45%). O principal objetivo deste trabalho é minimizar de maneira conjunta a energia consumida pelo módulo de ME/DE com relação às memórias externa e interna necessárias para a codificação MVC. A hierarquia de memória é composta por uma memória interna (a qual armazena a área de busca inteira), um controle dinâmico para a estratégia de power-gating da memória interna e um compressor de resultados parciais. Um controle de buscas foi proposto para explorar o comportamento da busca com o objetivo de atingir ainda mais reduções de energia. Além disso, este trabalho também agrega à hierarquia de memória um compressor de quadros de referência de baixa complexidade. A estratégia RCDR provê reduções de até 68% no consumo de energia quando comparada com estratégias estadoda- arte que são centradas no bloco atual da codificação. O compressor de resultados parciais é capaz de reduzir em 52% a comunicação com memória externa necessária para o armazenamento desses elementos. Quando comparada a técnicas de reuso de dados que não acessam toda área de busca, a estratégia RCDR também atinge os melhores resultados em consumo de energia, visto que acessos regulares a memórias externas DDR são energeticamente mais eficientes. O compressor de quadros de referência reduz ainda mais o número de acessos a memória externa (2,6 vezes menos acessos), aliando isso a perdas insignificantes na eficiência da codificação MVC. A memória interna requerida pela estratégia RCDR é até 74% menor do que estratégias centradas no bloco atual, como Level C. Além disso, o controle dinâmico para a técnica de power-gating provê reduções de até 82% na energia estática, o que é o melhor resultado entre os trabalho relacionados. A energia dinâmica é tratada pela técnica de união dos blocos candidatos, atingindo ganhos de mais de 65%. Considerando as reduções de consumo de energia atingidas pelas técnicas propostas neste trabalho, conclui-se que o sistema de hierarquia de memória proposto nesta dissertação atinge seu objetivo de atender às restrições impostas pela codificação MVC, no que se refere ao processamento do módulo de ME/DE. / This Master Thesis proposes a memory hierarchy for the Motion and Disparity Estimation (ME/DE) centered on the encoding references, called Reference-Centered Data Reuse (RCDR), focusing on energy reduction in the Multiview Video Coding (MVC). In the MVC encoders the ME/DE represents more than 98% of the overall energy consumption. Moreover, in the overall ME/DE energy, up to 90% is related to the memory issues, and only 10% is related to effective computation. The two items to be concerned with: (1) off-chip memory communication to fetch the reference samples (45%) and (2) on-chip memory to keep stored the search window samples and to send them to the ME/DE processing core (45%). The main goal of this work is to jointly minimize the on-chip and off-chip energy consumption in order to reduce the overall energy related to the ME/DE on MVC. The memory hierarchy is composed of an onchip video memory (which stores the entire search window), an on-chip memory gating control, and a partial results compressor. A search control unit is also proposed to exploit the search behavior to achieve further energy reduction. This work also aggregates to the memory hierarchy a low-complexity reference frame compressor. The experimental results proved that the proposed system accomplished the goal of the work of jointly minimizing the on-chip and off-chip energies. The RCDR provides off-chip energy savings of up to 68% when compared to state-of-the-art. the traditional MBcentered approach. The partial results compressor is able to reduce by 52% the off-chip memory communication to handle this RCDR penalty. When compared to techniques that do not access the entire search window, the proposed RCDR also achieve the best results in off-chip energy consumption due to the regular access pattern that allows lots of DDR burst reads (30% less off-chip energy consumption). Besides, the reference frame compressor is capable to improve by 2.6x the off-chip memory communication savings, along with negligible losses on MVC encoding performance. The on-chip video memory size required for the RCDR is up to 74% smaller than the MB-centered Level C approaches. On top of that, the power-gating control is capable to save 82% of leakage energy. The dynamic energy is treated due to the candidate merging technique, with savings of more than 65%. Due to the jointly off-chip communication and on-chip storage energy savings, the proposed memory hierarchy system is able to meet the MVC constraints for the ME/DE processing.

Made available in DSpace on 2014-06-11T19:31:40Z (GMT). No. of bitstreams: 0 Previous issue date: 2005-01-14Bitstream added on 2014-06-13T18:42:30Z : No. of bitstreams: 1 rossi_sr_dr_ilha.pdf: 2325960 bytes, checksum: 7ef7ad22ede243a4f480a84cc0e63023 (MD5) / Universidad Nacional de Asuncion / Atualmente, as redes de transdutores inteligentes desempenham um papel de importância vital em sistemas de Medição e Controle Distribuído. Nesse contexto, o Padrão IEEE 1451 para interfaceamento de transdutores inteligentes tem como objetivo simplificar a conectividade de transdutores em ambientes de rede, fornecendo, para tal fim, um conjunto de interfaces padronizadas, aumentando a flexibilidade dos sistemas de instrumentação distribuída. Neste trabalho descreve-se a implementação de um nó de rede em conformidade com o padrão IEEE 1451. O nó foi completamente desenvolvido através do emprego de ferramentas padronizadas e sistemas abertos. O nó é composto por um Processador de Aplicação com Capacidade de Operar em Rede (NCAP), com base no padrão IEEE 1451.1 e um Módulo de Interface para Transdutores Inteligentes (STIM), em conformidade com o padrão IEEE 1451.2. A parte física do NCAP foi implementada através dos recursos de um Computador Pessoal (PC) e de um Dispositivo Lógico Programável (PLD) de uso geral. A parte lógica do NCAP foi desenvolvida através da tecnologia Java. O STIM foi implementado com dispositivos lógicos programáveis versáteis, de uso geral, e sua funcionalidade foi integralmente descrita em linguagem de descrição de hardware. O conjunto NCAP-STIM foi conectado a uma rede de área local, sob o modelo de comunicação cliente-servidor, sendo que várias aplicações clientes podem acessar as informações dos transdutores conectados ao STIM, através da rede, via intermediação do NCAP. O emprego de ferramentas padronizadas e abertas no desenvolvimento total do sistema IEEE 1451 é uma das contribuições mais importantes do presente trabalho. No entanto, há várias contribuições pontuais como: a maneira de descrever as Informações de Transdutores em Formato Eletrônico (TEDS), a implementação... . / Nowadays, smart transducer networks play an essential role in distributed measurement and control systems. In this context, the IEEE 1451 smart transducer interface standards aimed to simplify transducer connectivity, providing a set of common interfaces for connecting transducers in a networked fashion, increasing the flexibility of distributed instrumentation systems. In this work the implementation of a network node according to the IEEE 1451 standard is introduced. The node has been fully developed using open and standardized tools. A Network Capable Application Processor (NCAP) according to the IEEE 1451.1 Standard and a Smart Transducer Interface Module (STIM) comprises the node. The physical part of the NCAP has been implemented using the resources of a Personal Computer (PC) and a general-purpose Programmable Logic Device (PLD). The logical part of the NCAP has been developed using Java technology. The STIM module was implemented with versatile, general-purpose Programmable Logic Devices. STIM functionality has been fully developed in hardware description language. A network node (STIM-NCAP) was connected in a client-server modelbased local area network. Many client applications can access STIM transducers information, through the network with the NCAP as an intermediary. One of the most important contributions of this work is the employment of open and standardized tools for implementing the IEEE 1451 network node. However, there are many specific contributions such as: Transducer Electronic Data Sheet (TEDS’s) description method, programmable logic-based Protocol Manager implementation that allows the use of the parallel port without any modification, the employment of low-cost PLDs for implementing the STIM and the Protocol Manager, and Java-based NCAP software development. Through the implementation of the IEEE Standard, industries... (Complete abstract, click electronic address below).