The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank.

The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank.

The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

No description available.

Yes / A tuneable slotted patch antenna design is presented and verified for use in the DCS, PCS and UMTS bands. The tuning circuit consists of two varactor diodes with some passive components, and is integrated fully with the r radiator patch, with the varactors occupying different locations over the slot. The tuning does not require any further modification to the patch or feed geometry. Good agreement is observed between the predicted and observed impedance bandwidth, return loss, gain and radiation pattern, throughout the range 1.70 GHz-2.05 GHz.

Yes / A tunable band-notch printed monopole antenna is presented, exhibiting a wide impedance bandwidth from 1.5 to 5.5 GHz with good impedance matching (VSWR ≤ 2) and a tunable rejected frequency band from 2.38 to 3.87 GHz. The band-notching is achieved by adding an inner chorded crescent element within a driven element of a similar shape. By varying the value of the varactor which is placed between the inner and outer arcs, the desired variable rejected can be obtained. Simulated and measured results show wide impedance bandwidth with a tunable band notch, stable radiation patterns, and consistent nearly constant gain. The antenna is suitable for mobile and portable applications.

Yes / Currently, several microwave filter designs contend for use in wireless communications. Among various microstrip filter designs, the reconfigurable planar filter presents more advantages and better prospects for communication applications, being compact in size, light-weight and cost-effective. Tuneable microwave filters can reduce the number of switches between electronic components. This paper presents a review of recent reconfigurable microwave filter designs, specifically on current advances in tuneable filters that involve high-quality factor resonator filters to control frequency, bandwidth and selectivity. The most important materials required for this field are also highlighted and surveyed. In addition, the main references for several types of tuneable microstrip filters are reported, especially related to new design technologies. Topics surveyed include microwave and millimetre wave designs for 4G and 5G applications, which use varactors and MEMSs technologies. / This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement H2020-MSCA-ITN-2016 SECRET-722424.

No description available.

Yes / In this work, miniaturized tunable two-antenna MIMO systems composed of printed F-slot shaped is developed to operate in the GPS, PCS, DCS and UMTS bands. The two-element MIMO antenna occupies a volume of 50 × 37.5 ×1.6 mm3, and is printed on an FR4 substrate. Initially, the frequency tunability of the MIMO antennas was verified by lumped capacitors with values between 0.75 to 2.75 pF to achieve a tuning range from 1.55 to 2.07GHz while the low mutual coupling between the radiators was accomplished by adding an I-shaped branch to a cut-away ground plane. The two antennas are then loaded with varactors to simultaneously achieve miniaturization and tunability. Simulation and measurement results demonstrate the successful implementation of a tunable MIMO with coupling reduction mechanism for a portable handheld wireless transceiver. The channel capacity of the proposed antenna is investigated and found to be close to that of an un-correlated system with efficient diversity in which the mutual coupling across the full bandwidth was better than -13dB. Owing to the compact size and ease of manufacture, the proposed antennas can be a promising solution for adaptive MIMO systems in handheld devices. / This work has been performed in the framework of ARTEMOS project under work programme ENIAC JU 2010 and FCT (Fundação para a Ciência e Tecnologia) .The authors would like to thank Datong PLC (Leeds LS18 4EG, West Yorkshire, U.K.), for their financial support of the Knowledge Transfer Partnership (KTP No: 008734).

Yes / Four versions of the compact hexagonal-shaped monopole printed antennas for UWB applications are presented. The first proposed antenna has an impedance bandwidth of 127.48 % (3.1 GHz to 14 GHz), which satisfies the bandwidth for ultra-wideband communication systems. To reduce the foreseen co-channel interference with WLAN (5.2GHz) and X-Band systems (10GHz), the second and third antennas type were generated by embedding hexagonal slot on the top of the radiating patch. The integration of the half and full hexagonal slots created notched bands that potentially filtered out the sources of interference, but were static in nature. Therefore, a fourth antenna type with tuneable-notched bands was designed by adding a varactor diode at an appropriate location within the slot. The fourth antenna type is a dual-notch that was electronically and simultaneously tuned from 3.2GHz to 5.1GHz and from 7.25GHz up to 9.9GHz by varying the bias voltages across the varactor. The prototypes of the four antenna versions were successfully fabricated and tested. The measured results have good agreement with the simulated results. / This work is carried out under the grant of the Fundacão para a Ciência e a Tecnologia (FCT - Portugal), with the reference number: SFRH/BPD/95110/2013.