Yes / Four versions of the compact hexagonal-shaped monopole printed antennas for UWB applications are presented. The first proposed antenna has an impedance bandwidth of 127.48 % (3.1 GHz to 14 GHz), which satisfies the bandwidth for ultra-wideband communication systems. To reduce the foreseen co-channel interference with WLAN (5.2GHz) and X-Band systems (10GHz), the second and third antennas type were generated by embedding hexagonal slot on the top of the radiating patch. The integration of the half and full hexagonal slots created notched bands that potentially filtered out the sources of interference, but were static in nature. Therefore, a fourth antenna type with tuneable-notched bands was designed by adding a varactor diode at an appropriate location within the slot. The fourth antenna type is a dual-notch that was electronically and simultaneously tuned from 3.2GHz to 5.1GHz and from 7.25GHz up to 9.9GHz by varying the bias voltages across the varactor. The prototypes of the four antenna versions were successfully fabricated and tested. The measured results have good agreement with the simulated results. / This work is carried out under the grant of the Fundacão para a Ciência e a Tecnologia (FCT - Portugal), with the reference number: SFRH/BPD/95110/2013.

The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors. This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 μm single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed. / Master of Science

La croissance rapide du marché des télécommunications a conduit à une augmentation significative du nombre de bandes de fréquences allouées et à un besoin toujours plus grand en terminaux offrant un accès à un maximum de standards tout en proposant un maximum de services. La miniaturisation de ces appareils, combinée à la mise en place de fonctions supplémentaires, devient un vrai challenge pour les industriels. Une solution consiste à utiliser des fonctions hyperfréquences accordables (filtres, commutateurs, amplificateurs,…). A ce jour, trois technologies d'accord sont principalement utilisées : capacités variables, matériaux agiles ou encore MEMS RF. Dans le cadre de cette thèse, nous avons travaillé sur l’optimisation de dispositifs hyperfréquences reconfigurables en utilisant des couches minces ferroélectriques KTN et des diodes varactor. Nos premiers travaux étaient relatifs à l’optimisation des dispositifs hyperfréquences accordables à base de couche minces KTN. Dans ce sens, nous avons tout d’abord caractérisé le matériau KTN en basse et haute fréquence afin de déterminer ses caractéristiques diélectriques et ses caractéristiques en température. Nous avons ensuite réalisé des dispositifs hyperfréquence élémentaires tels des capacités interdigitées et des déphaseurs à base de KTN. Leurs performances ont alors été comparées aux mêmes dispositifs réalisés cette fois à base de la solution la plus utilisée BST. Bien qu’un léger avantage soit acquis à la solution BST, il n’en reste pas moins vrai que les résultats avec le matériau KTN sont très proches indiquant que cette voie peut également, après optimisation, apporter une alternative au BST. La seconde partie de nos travaux concerne la réalisation de filtres planaires accordables en fréquence à base de matériaux KTN et de diodes varactor. Nous avons ainsi réalisé deux filtres passe-bande accordables. Un premier filtre passe-bande de type « open loop » possédant deux pôles agiles en fréquence centrale et un second filtre passe-bande de type SIR rendant possible l’accord de sa fréquence centrale ainsi que de sa bande passante à partir de diodes varactor. Lors de la conclusion sur nos travaux, nous évoquons les suites à donner à ce travail et les perspectives. / The rapid growth of the telecommunications industry has led to a significant increase in the number of allocated frequency bands and a growing need for terminals providing access to an increasing number of standards while offering maximum services. The miniaturization of these devices combined with the implementation of additional functions has become a real challenge for the industry. The use of tunable microwave functions (filters, switches, amplifiers ...) appears as a solution to this issue. In this way, three main technologies are mainly used: variable capacitors, tunable materials and RF MEMS. Within the scope of this thesis work, our investigations focused on tunable microwave devices optimization through the use of KTN ferroelectric thin films and varactor diodes. The first part of our study deals with the optimization of tunable microwave devices based on KTN ferroelectric thin films. In this way, we initially characterized KTN material in low and high frequency to determine its dielectric properties and characteristics according to the temperature. Then, we designed basic microwave devices such as interdigitated capacitors and phase shifters based on KTN thin films. Their performances were then compared with BST solution. Despite results highlighting a slight advantage to BST solution, KTN material, after optimization process, could be a BST alternative solution. In a second part, our work focused on the realization of tunable planar filters based on KTN materials and varactor diodes. We made two tunable bandpass filters. The first one is a center frequency tunable bandpass two pole open loop filter and the second one is a center frequency and bandwidth tunable SIR bandpass filter using varactor diodes. Finally, we discussed follow-up to give to this work and outlooks.

Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power amplifier and linearizer design techniques. Dynamically varying the load impedance and bias point of a transistor according to the varying envelope of the incoming RF signal also known as Dynamic Load Modulation (DLM) and Dynamic Supply Modulation (DSM), respectively, are two separate methods for improving the efficiency in power amplifier design. In this dissertation, a combination of both variable gate bias and tunable load concepts is applied in an amplifier structure consisting of two transistors in parallel. A novel computer aided design methodology is proposed for careful selection of the load and biasing points of the individual transistors. The method which is based on load-pull analysis performs sweeps on the gate bias voltages of the active devices and input drive level of the amplifier in order to obtain ranges of biases that result in the generation of IMD sweet spots. Following that, the amplifier is designed employing the load line theory and bias switching at the same time in order to enhance the efficiency in reduced drive levels while extending the output 1 dB compression point to higher values at higher drives. Tunable matching networks are implemented utilizing varactor stacks in a &Pi / con

Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power ampli

The work was based on digitally controlled oscillator for an all-digital PLL in 65nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existinggeneration, there has to be quick development with the technique. In such case ananalog PLL which was used earlier gradually getting converted to digital circuit.All-digital PLL blocks does the same work as an analog PLL blocks, but thecircuits and other control circuitry designed were completely in digital form, becausedigital circuit has many advantages over analog counterpart when they arecompared with each other. Digital circuit could be scaled down or scaled up evenafter the circuits were designed. It could be designed for low power supply voltageand easy to construct in a 65 nm process. The digital circuit was widely chosento make life easier. In most of the application PLL’s were used for clock and data recovery purpose,from that perspective jitter will stand as a huge problem for the designers. Themain aim of this thesis was to design a DCO that should bring down the jitter asdown as possible which was designed as standalone, the designed DCO would belater placed in an all-digital PLL. To understand the concept and problem aboutjitter at the early stage of the project, an analog PLL was designed in block leveland tested for different types of jitter and then design of a DCO was started. This document was about the design of a digitally controlled oscillator whichoperates with the center frequency of 2.145 GHz. In the first stage of the projectthe LC tank with NMOS structure was built and tested. In the latter stage the LCtank was optimized by using PMOS structure as negative resistance and eventuallyended up with NMOS and PMOS cross coupled structure. Tuning banks were oneof the main design in this project which plays a key role in locking the system ifthe DCO is placed in an all-digital PLL system. So, three types of tuning bankswere introduced to make the system lock more precisely. The control circuits andthe varactors built were all digital and hence it is called as digitally controlledoscillator. Digital control circuits, other sub-blocks like differential to single endedand simple buffers were also designed to optimize the signal and the results wereshown.DCO and tuning banks were tested using different types of simulation and were tested for different jitter qualities and analysis. The simulation results are shownin the final chapter simulation and results.

Micro-Electro-Mechanical Systems (MEMS) varactors have the potential to replace conventional varactor diodes, due to their high loss and non-linearity, in many applications such as phase shifters, oscillators, and tunable filters. The objective of this thesis is to develop novel MEMS varactors to improve the capacitance tuning ratio, linearity, and quality factor. Several novel varactor configurations are developed, analyzed, fabricated and tested. They are built by using standard MEMS fabrication processes, as well as monolithic integration techniques in CMOS technology. The first capacitor consists of two movable plates, loaded with a nitride layer that exhibits an analog continuous capacitance tuning ratio. To decrease the the parasitic capacitance, a trench in the silicon substrate under the capacitor is adopted. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitors’ tuning ratio. Experimental and theoretical results are presented for two versions of the proposed capacitor with different capacitance values. The measured capacitance tuning ratio is 280% at 1 GHz. The proposed MEMS vararctor is built using the MetalMUMPs process. The second, third, and fourth capacitors have additional beams that are called carrier beams. The use of the carrier beams makes it possible to obtain an equivalent nonlinear spring constant, which increases the capacitors’ analog continuous tuning ratio. A lumped element model and a continuous model of the proposed variable capacitors are developed. The continuous model is simulated by commercial software. A detailed analysis for the steady state of the capacitors is presented. The measured capacitance tuning ratios of these three capacitors are 410%, 400% and 470%, respectively at 1 GHz. Also, the selfresonance frequency is measured and found to exceed 11 GHz. The proposed MEMS variable capacitors are built by the PolyMUMPs process. The fifth novel parallel-plate MEMS varactor has thin-film vertical comb actuators as its driver. Such an actuator can vertically displace both plates of the parallel-plate capacitor. By making use of the fringing field, this actuator exhibits linear displacement behavior, caused by the induced electrostatic force of the actuator’s electrodes. The proposed capacitor has a low parasitic capacitance and linear deflection due to the mechanically connected and electrically isolated actuators to the capacitor’s parallel-plates. The measured tuning capacitance ratio is 7:1 (600%) at 1 GHz. The fabricated MEMS varactor exhibits a self resonance frequency of 9 GHz and built by MetalMUMPs process. The sixth parallel-plate MEMS varactor exhibits a linear response and high tuning capacitance ratio. The capacitor employs the residual stress of the chosen bi-layer, and the non-linear spring constants from the suspended cantilevers to obtain a non-linear restoring force that compensates for the nonlinear electrostatic force induced between the top and bottom plates. Two existing techniques are used to widen the tuning range of the proposed capacitor. The first technique is to decrease the parasitic capacitance by etching the lossy substrate under the capacitor’s plates. The second technique is employed to increase the capacitance density, where the areas between the top and bottom plates overlap, by applying a thin film of dielectric material, deposited by the atomic layer deposition (ALD) technique. The measured linear continuous tuning ratio for the proposed capacitor, built in the PolyMUMPs process, is 5:1 (400%). The seventh and eighth MEMS variable capacitors have plates that curl up. These capacitors are built in 0.35 μm CMOS technology from the interconnect metallization layers. The plates of the presented capacitors are intentionally curled upward to control the tuning performance. A newly developed maskless post-processing technique that is appropriate for MEMS/CMOS circuits is proposed. it consists of dry and wet etching steps, developed to integrate the proposed MEMS varactors in CMOS technology. Mechanically, the capacitors are simulated by the finite element method in ANSYS, and the results are compared with the measured results. The seventh capacitor is a tri-state structure that exhibits a measured tuning range of 460% at 1 GHz with a flat capacitance response that is superior to that of conventional digital capacitors. The proposed capacitor is simulated in HFSS and the extracted capacitance is compared with the measured capacitance over a frequency range of 1 GHz to 5 GHz. The eighth capacitor is an analog continuous structure that demonstrates a measured continuous tuning range of 115% at 1 GHz with no pull-in. The measured quality factor for both CMOSbased capacitors is more than 300 at 1.5 GHz. The proposed curled-plate capacitors have a small area and can be realized to build a System-on-Chip (SoC). Finally, a tunable band pass filter that utilizes the MEMS variable capacitors in 0.18 μm CMOS technology from TSMC is designed, modeled and fabricated.

Micro-Electro-Mechanical Systems (MEMS) varactors have the potential to replace conventional varactor diodes, due to their high loss and non-linearity, in many applications such as phase shifters, oscillators, and tunable filters. The objective of this thesis is to develop novel MEMS varactors to improve the capacitance tuning ratio, linearity, and quality factor. Several novel varactor configurations are developed, analyzed, fabricated and tested. They are built by using standard MEMS fabrication processes, as well as monolithic integration techniques in CMOS technology. The first capacitor consists of two movable plates, loaded with a nitride layer that exhibits an analog continuous capacitance tuning ratio. To decrease the the parasitic capacitance, a trench in the silicon substrate under the capacitor is adopted. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitors’ tuning ratio. Experimental and theoretical results are presented for two versions of the proposed capacitor with different capacitance values. The measured capacitance tuning ratio is 280% at 1 GHz. The proposed MEMS vararctor is built using the MetalMUMPs process. The second, third, and fourth capacitors have additional beams that are called carrier beams. The use of the carrier beams makes it possible to obtain an equivalent nonlinear spring constant, which increases the capacitors’ analog continuous tuning ratio. A lumped element model and a continuous model of the proposed variable capacitors are developed. The continuous model is simulated by commercial software. A detailed analysis for the steady state of the capacitors is presented. The measured capacitance tuning ratios of these three capacitors are 410%, 400% and 470%, respectively at 1 GHz. Also, the selfresonance frequency is measured and found to exceed 11 GHz. The proposed MEMS variable capacitors are built by the PolyMUMPs process. The fifth novel parallel-plate MEMS varactor has thin-film vertical comb actuators as its driver. Such an actuator can vertically displace both plates of the parallel-plate capacitor. By making use of the fringing field, this actuator exhibits linear displacement behavior, caused by the induced electrostatic force of the actuator’s electrodes. The proposed capacitor has a low parasitic capacitance and linear deflection due to the mechanically connected and electrically isolated actuators to the capacitor’s parallel-plates. The measured tuning capacitance ratio is 7:1 (600%) at 1 GHz. The fabricated MEMS varactor exhibits a self resonance frequency of 9 GHz and built by MetalMUMPs process. The sixth parallel-plate MEMS varactor exhibits a linear response and high tuning capacitance ratio. The capacitor employs the residual stress of the chosen bi-layer, and the non-linear spring constants from the suspended cantilevers to obtain a non-linear restoring force that compensates for the nonlinear electrostatic force induced between the top and bottom plates. Two existing techniques are used to widen the tuning range of the proposed capacitor. The first technique is to decrease the parasitic capacitance by etching the lossy substrate under the capacitor’s plates. The second technique is employed to increase the capacitance density, where the areas between the top and bottom plates overlap, by applying a thin film of dielectric material, deposited by the atomic layer deposition (ALD) technique. The measured linear continuous tuning ratio for the proposed capacitor, built in the PolyMUMPs process, is 5:1 (400%). The seventh and eighth MEMS variable capacitors have plates that curl up. These capacitors are built in 0.35 μm CMOS technology from the interconnect metallization layers. The plates of the presented capacitors are intentionally curled upward to control the tuning performance. A newly developed maskless post-processing technique that is appropriate for MEMS/CMOS circuits is proposed. it consists of dry and wet etching steps, developed to integrate the proposed MEMS varactors in CMOS technology. Mechanically, the capacitors are simulated by the finite element method in ANSYS, and the results are compared with the measured results. The seventh capacitor is a tri-state structure that exhibits a measured tuning range of 460% at 1 GHz with a flat capacitance response that is superior to that of conventional digital capacitors. The proposed capacitor is simulated in HFSS and the extracted capacitance is compared with the measured capacitance over a frequency range of 1 GHz to 5 GHz. The eighth capacitor is an analog continuous structure that demonstrates a measured continuous tuning range of 115% at 1 GHz with no pull-in. The measured quality factor for both CMOSbased capacitors is more than 300 at 1.5 GHz. The proposed curled-plate capacitors have a small area and can be realized to build a System-on-Chip (SoC). Finally, a tunable band pass filter that utilizes the MEMS variable capacitors in 0.18 μm CMOS technology from TSMC is designed, modeled and fabricated.

Post-fabrication tuning of filters is usually realized by adding number of elements for tuning the frequency and/or controlling the couplings between the resonators. The task of these tuning elements is to control resonators center frequency, inter-resonators coupling and input/output couplings. While the most common tool for the post-fabrication tuning is to use tuning screws and rods, it is not usually practical to tune a planar filter with these tools. This thesis introduces a novel method for global post-fabrication tuning of microwave filters by designing and adding a passive distributed-element circuit in parallel to the detuned filter. The idea, which is demonstrated by experimental results, has several advantages over traditional techniques for filter tuning that use screws. The quality factor of resonator reduces significantly after adding the tuning screws while the proposed method does not affect the Q of resonators. The most important advantage of the proposed compensator circuit is that it can be employed without knowing details of the detuned filters. Since the compensator circuit will be added in parallel to the detuned filter, it will not affect the elements of filter individually. So whether the filter is planar or cavity, the proposed circuit can be used for the tuning. The experimental results obtained demonstrate the validity of this method. The dissertation also presents a novel concept for designing a center frequency and bandwidth tunable microstrip filter by using GaAs varactors. The proposed isolated coupling structure which is used in this filter makes the bandwidth tuning possible by reducing the loading effect of coupling elements on the resonators. The center frequency of this filter can be also tuned by using a different set of varactors connected to resonators. A 3-pole filter based on this concept has been designed and simulated. The concept can be expanded to higher order filters.

Post-fabrication tuning of filters is usually realized by adding number of elements for tuning the frequency and/or controlling the couplings between the resonators. The task of these tuning elements is to control resonators center frequency, inter-resonators coupling and input/output couplings. While the most common tool for the post-fabrication tuning is to use tuning screws and rods, it is not usually practical to tune a planar filter with these tools. This thesis introduces a novel method for global post-fabrication tuning of microwave filters by designing and adding a passive distributed-element circuit in parallel to the detuned filter. The idea, which is demonstrated by experimental results, has several advantages over traditional techniques for filter tuning that use screws. The quality factor of resonator reduces significantly after adding the tuning screws while the proposed method does not affect the Q of resonators. The most important advantage of the proposed compensator circuit is that it can be employed without knowing details of the detuned filters. Since the compensator circuit will be added in parallel to the detuned filter, it will not affect the elements of filter individually. So whether the filter is planar or cavity, the proposed circuit can be used for the tuning. The experimental results obtained demonstrate the validity of this method. The dissertation also presents a novel concept for designing a center frequency and bandwidth tunable microstrip filter by using GaAs varactors. The proposed isolated coupling structure which is used in this filter makes the bandwidth tuning possible by reducing the loading effect of coupling elements on the resonators. The center frequency of this filter can be also tuned by using a different set of varactors connected to resonators. A 3-pole filter based on this concept has been designed and simulated. The concept can be expanded to higher order filters.