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1	Compilation efficace pour FPGA reconfigurable dynamiquement Bergeron, Étienne January 2008 (has links) Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal. Synthèse dynamique JIT Virtex-II-Pro Bitstream FPGA
2	Compilation efficace pour FPGA reconfigurable dynamiquement Bergeron, Étienne January 2008 (has links) Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal Synthèse dynamique JIT Virtex-II-Pro Bitstream FPGA
3	Implementation and Design of a Bit-Error Generator and Logger for Multi-Gigabit Serial Links Botella, Pedro January 2006 (has links) <p>Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher</p><p>speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,</p><p>this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need</p><p>to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors</p><p>in a controlled way.</p><p>A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been</p><p>developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the</p><p>hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is</p><p>handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links,</p><p>independently. This report describes the implementation and the necessary theoretical background for this.</p> Bit Error Generation Fibre Channel Implementation FPGA Virtex II Pro Computer engineering Datorteknik
4	Implementation and Design of a Bit-Error Generator and Logger for Multi-Gigabit Serial Links Botella, Pedro January 2006 (has links) Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer, this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors in a controlled way. A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links, independently. This report describes the implementation and the necessary theoretical background for this. Bit Error Generation Fibre Channel Implementation FPGA Virtex II Pro Computer Engineering Datorteknik
5	Parallel Genetic Algorithm Engine on an FPGA La Spina, Mark 05 April 2010 (has links) The field of FPGA design is ever-growing due to costs being lower than that of ASICs, as well as the time and cost of development. Creating programs to run on them is equally important as developing the devices themselves. Utilizing the increase in performance over software, as well as the ease of reprogramming the device, has led to complex concepts and algorithms that would otherwise be very time-consuming when implemented on software. One such focus has been towards a search and optimization algorithm called the genetic algorithm. The proposed approach is to take an existing application of the genetic algorithm on an FPGA, developed by Fernando et al. [1], and create several instances of it to make a parallel genetic algorithm engine. The genetic algorithm cores are interfaced with a controller module that will control the flow of data between them to implement the parallel execution. Both coarse-grained and fine-grained parallelism are tested and results collected to find the best performance when compared to the single core design. Initial experimental results show some improvement over the number of generations required to reach the optimal fitness level, as well as more significant improvement for the number of generations needed for the average fitness to reach the optimal level. Field Programmable Gate Array Reconfigurable Logic Evolutionary Algorithms Verilog Xilinx Virtex-II Pro American Studies Arts and Humanities
6	Implementace generického procesoru v FPGA / Implementation of Generic Processor in FPGA Mikušek, Petr Unknown Date (has links) This thesis studies processor architectures suitable for embedded processors. This includes Transport Triggered Architectures (TTA). TTA is programmed by specifying data transport; operations are triggered as a side effect of data transports. In traditional Operation Triggered Architectures (OTA) requested operations are determined by program. Data transports are handled internally by hardware so it's impossible to control and optimize data transfer by compiler. This approach brings an advantage of hardware and software aspects. The aim of this thesis is to design and implement a sample TTA processor in VHDL followed by realization in FPGA. This processor is designed in a generic manner, i.e. customized by set of generic parameters such as data width, number of buses, etc.
7	BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs Morford, Casey Justin 03 January 2006 (has links) With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow. / Master of Science Field programmable gate arrays Partial Reconfiguration Virtex-II Pro Bitstream Manipulation Bitstream Xilinx Virtex-II Dynamic Module Server
8	Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGA Iqbal, Rashid January 2006 (has links) <p>This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.</p> Bidirectional motion estimation FPGA Relationally placed macro CLB slice tristate buffers comparator pipelining search upper search lower VHDL Xilinx block matching MeEngine LMC CMC. sum of absolute differences systolic array SARow PE2X8 MeProC 125 MHz Virtex II Pro Electronics Elektronik
9	Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGA Iqbal, Rashid January 2006 (has links) This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain. Bidirectional motion estimation FPGA Relationally placed macro CLB slice tristate buffers comparator pipelining search upper search lower VHDL Xilinx block matching MeEngine LMC CMC. sum of absolute differences systolic array SARow PE2X8 MeProC 125 MHz Virtex II Pro Electronics Elektronik

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