A radio transceiver has been designed and built for a W-CDMA experimental system operating at 2GHz. The radio is an RF front-end for mobile terminals. The radio provides the functions of modulation and demodulation to enable transmitting and receiving digital information through the air link. The radio comprises one transmitter in conjunction with transmit power control (TPC), two independent receivers in conjunction with automatic gain control (AGC) and automatic frequency control (AFC), and one common synthesizer. Data exchange between the radio and the baseband processor takes place in an 8-bit digital format. Digital-to-analog converters (DAC) at the transmitter and analog- to-digital converters (ADC) at the receivers provide the interface between the radio and the baseband processor. DACs are also used to convert the 7-bit command codes from the processor to analog signals for the TPC, AGC and AFC. The radio transceiver is designed to meet the stringent requirements imposed by the W-CDMA system. The 70dB TPC enables the adaptive power control for combating the near-far problem. The high linearity of the transmitter provides the use of linear modulation with less than 40dBc adjacent channel power suppression. The 0.03125ppm tuning resolution of the AFC maximizes the receiver sensitivity. The 80dB AGC produces a constant demodulated signal level to the ADC regardless of the RF signal level. This thesis documents the design methodology for this radio transceiver. / Master of Science

Depuis la première génération de téléphone mobile, de nombreuses fonctions et outils ont été intégrés dans nos terminaux. Il y a vingt ans, nous utilisions nos téléphone pour émettre des appels et envoyer/recevoir des messages. Aujourd’hui, l’accès à internet, la radio, l’appareil photo, des jeux et de la musique sont des fonctionnalités que l’on retrouve dans nos téléphones mobiles.Dans un contexte de téléphonie pouvant adresse plusieurs standards, l’objectif de cette thèse est de concevoir et de réaliser l’implémentation d’une architecture capable d’améliorer la linéarité de notre émetteur pour le standard 3G, utilisant des composants analogiques et numériques. Pour cela, notre étude se concentrera sur l’amélioration de la linéarité, tout en maintenant une consommation la plus faible possible mais également tout en évitant d’augmenter la taille d’une puce 3G. Nous allons démontrer qu’il est possible d’intégrer une technique de linéarisation tout en maintenant une consommation et une surface en silicium.Le premier chapitre présente différentes architectures d’émetteurs et des techniques de linéarisation avec leurs avantages et inconvénients. Il est également présenté des moyens d’évaluer l’efficacité d’un émetteur par des simulations ou des mesures. L’objectif de cette partie est de choisir une technique de linéarisation à laquelle nous associerons une architecture d’émetteur afin de répondre le plus rigoureusement à notre application et ces contraintes émanant.Le second chapitre détaille le fonctionnement du système complet, la partie numérique et la partie analogique, s’appuyant sur des études théoriques. Nous commencerons en détaillant les contraintes et les précautions qui doivent être prises en compte par le concepteur afin d’étudier l’instabilité et le bruit produit par l’émetteur. Nous décrierons alors deux algorithmes numériques permettant de réaliser la correction des signaux. Des simulations au niveau système de la boucle Cartésienne seront également présenté utilisant, dans un premier temps un amplificateur de puissance idéal, pour ensuite utilisé un amplificateur de puissance réalisé en technologie BiCMOS, et finalement un amplificateur de puissance conçu en technologie CMOS, qui est celle choisie pour notre étude.Le troisième chapitre présente la synthèse de la partie numérique en technologie CMOS des deux algorithmes précédemment cités, elle prend en compte toutes les étapes ; du code VHDL jusqu’au layout, permettant de réaliser un circuit numérique. Ensuite, il est décrit chaque composant de la boucle cartésienne, avec leurs propres simulations ou mesures. De plus, il est important de garder à l’esprit que l’objectif de cette thèse repose sur l’intégration du système complet (partie analogique et numérique) en technologie CMOS 65nm de STMicroelectronics, démontrant ainsi la faisabilité de la solution.Dans un premier temps, nous décrirons la partie numérique permettant de réaliser les étapes de correction de phase et de soustraction des signaux en technologie ASIC. L’algorithme de CORDIC a pour avantage de minimiser la consommation et l’occupation en Silicium de la partie analogique. Par la suite, l’architecture et les spécifications de chaque brique de base constituant la partie analogique seront présentées. Dans notre cas, la chaîne directe est composée de filtres, de mélangeurs, et d'un amplificateur de puissance. Notre objectif est de réaliser ces trois fonctions avec le minium de consommation et une surface du circuit la plus faible possible, ceci permettant une intégration plus aisée.Finalement, les simulations système seront présentées utilisant le logiciel de simulation ADC (Advanced Design Software) d’Agilent pour la partie analogique. Des co-simulations ont été réalisées sur le système complet, utilisant SystemVue pour la partie numérique. Les simulations réalisant ADS nous ont fourni les performances de chaque brique de base s’appuyant sur les caractéristiques des transistors. / Since the first generation of mobile phones, a lot of functions, standards and tools have been integrated on handsets. Twenty years ago, consumers could use their mobile phones only to call and to send messages. Nowadays, internet access, radio, cameras, games and music are included and available as options for every mobile phone.All of these new services make the cost of production for a cellular phone more expensive. Despite that, industry has to find a solution to maintain their products the most attractive as possible including the large range of integrated functions.In the context of interaction with other standards, the aim of this thesis is to design and implement a chipset able to improve the linearity of a transmitter for third generation mobile phones, using both digital and analog technologies. For this purpose, the study will focus on the improvement of the linearity, keeping the consumption and the die area of the circuit as small as possible. We will prove that linearization on an integrated circuit is possible with almost the same consumption and die area occupation compared to a classic transmitter.The first chapter presents the different architectures used for a transmitter and various linearization techniques with their advantages and drawbacks. Some metrics are also presented in order to evaluate these architectures. The goal of this part is to choose a linearization technique associated to a transmitter in order to fit with our application and constraints.The second chapter explains the complete system, digital and analog parts, with theoretical studies. We will start by detailing the constraints and precautions that must be taken into account by the designer to study the instability and the noise generated by the transmitter. We will describe how two algorithms make signal corrections. In the last part we will show system level simulations of the Cartesian Feedback using, first, an ideal power amplifier (PA), then, a PA in a BiCMOS technology, and finally, a PA in a CMOS technology that will be used for the final integrated circuit.The third and last chapter shows the digital synthesis in a CMOS technology of the two algorithms previously mentioned, considering all steps, from the VHDL code until the layout of the digital part. We will describe and simulate each analog building block of the Cartesian Feedback, with the measurement results for some of them. Each chapter will be working towards the goal of this study, demonstrated in this part: to make an integrated system, with its complete solution and simulations.This chapter presents the integration of the analog and digital Cartesian Feedback described previously in 65nm CMOS technology from STMicroelectronics. First, the digital part generating the phase correction and subtraction will be shown in ASIC technology, with a CORDIC algorithm to reduce its consumption and size. Secondly, the architecture and specification of building blocks will be shown. In our case, the direct path is composed of filters, RF modulator and a Power Amplifier. Our objective is to design these three functions to minimize the consumption and the silicon area of the integrated architecture. Finally, system level simulations will be presented using the ADS (Advanced Design Software) from Agilent for the analog part. Co-simulations have been done to analyze the whole system, with SystemVue for the digital part. The simulations using ADS will provide the performance of each building block on the transistors level.

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / With the recent broadband upgrades to various cellular infrastructures and the myriad new emerging wireless broadband standards and services offered by carriers, it is often difficult to navigate this sea of technology. In deciding the best choice for broadband telemetry applications, one must look not only at the technology, but also at the economics, market timing, bandwidths, legacy issues, future expandability and coverage, security, protocols, and the requirements of the specific application. This paper reviews the technology roadmap of cellular providers keeping these issues in perspective as they apply to TCP/IP data for images, audio, video, and other broadband telemetry data using CDMA 1xRTT, EV-DO, and EV-DO Rev A systems as well as GSM GPRS/EDGE, UMTS/W-CDMA, HSDPA, and HSUPA networks. Lastly, issues seen by system integrators when using cellular channels for telemetry applications are examined, and a case is presented for overcoming many of these issues through the use of cellular routers.

Ce mémoire porte sur la conception de l'interface numérique s'occupant, lors de la réception au sein d'un système de transmission de données, des problèmes d'accès au canal dans les protocoles large bande de type W-CDMA (Wideband Code Division Multiple Access / Multiplexage à large bande par code). Le cœur de la problématique se situe dans la partie numérique en bande de base, le récepteur RAKE. Ce récepteur est responsable de la démodulation du signal et de l'exploitation de la diversité du signal en identifiant et combinant les composantes de trajets multiples d'un même signal. En effet, cette dernière fonction est particulièrement importante d’une part de son rôle pour contrer les effets d'évanouissement causés par les trajets multiples, et d’autre part du rôle central du récepteur RAKE. La conception et l'implantation de celui-ci revêtent un caractère primordial. Dans ce mémoire, nous proposons une nouvelle architecture pour le récepteur RAKE : CodeRAKE. Les caractéristiques architecturales principales recherchées sont une grande flexibilité et une extensibilité aisée, tout en préservant la fonctionnalité et un bon équilibre entre ressources utilisées (et donc surface consommée) et performances (vitesse de fonctionnement). Pour satisfaire les contraintes de flexibilité et d'extensibilité, l'architecture CodeRAKE est partitionnée (pour être modulaire) en fonction du nombre d'utilisateurs et du nombre de codes par utilisateur, sans perdre de vue les contraintes de limitions de ressources utilisées et de préservation des performances. La modularité élevée de CodeRAKE permet l'application aisée de techniques de parallélisation permettant d'augmenter facilement les performances pour satisfaire notamment les besoins du côté de la station de base. L'approche architecturale mise en œuvre est souple et peut être facilement adaptée à d'autres protocoles existants ou futurs. Elle répond ainsi au défi des années à venir, où les récepteurs devront être capables de supporter de multiples protocoles et interfaces d'accès, notamment sous le contrôle de couches logicielles / This thesis focuses on the design of the air interface of W-CDMA (Wideband Code Division Multiple Access) systems, particularly on the aspects related to the channel access problems at the reception side. The main concern herein is the design of the baseband digital parts, that is, the RAKE receiver. This receiver is in charge of the signal demodulation and responsible for making profit of signal diversity. This late functionality is particularly important as it allows to counter signal fading by detecting and combining multipath components (leading to signal reinforcement) Given the central role of the RAKE receiver, its design and implementation are of paramount importance. In this thesis, we propose a new architecture for the RAKE receiver: CodeRAKE. The main architectural characteristics being aimed are high flexibility and scalability, yet preserving a good trade-off between resource use (and hence, area consumption) and performance (operation speed). In order to satisfy the flexibility and scalability constraints, the CodeRAKE architecture is modular and partitioned according to the number of users and the number of codes per user, with the resource limitation and performance preservation constraints in mind. The high levels of modularity of the CodeRAKE architecture allow an easy use of parallelisation techniques, which in turn allow an easy increase of performances, particularly at the base station side.The architectural approach proposed herein are versatile and can be easily adapted to other existing or future protocols. It responds to the challenge of the coming years, where the receiver will have to support multiple protocols and access interfaces, including control software layers

In recent years, mobile communications have become affordable and popular. High cellular capacity in terms of number of users and data-rates is in need. As the available frequency spectrums for mobile communications are limited, the utilization of the radio resources to achieve high capacity without imposing high equipment cost is of utmost importance. Recently, multi-hop cellular networks (MCNs) were introduced. These networks have the potential of enhancing the cell capacity and extending the cell coverage at low extra cost. However, in a cellular network, the cell or system capacity is inversely related to the cell size. In MCNs, the cell size, the network density and topology affect the coverage of source nodes and the total demands that can be served and, thus, the system throughput. Although the cell size is an important factor, it has not been exploited for maximizing throughput. Another major issue in MCNs is the increase in packet delay because multi-hopping is involved. High packet delay affects quality of service provisioning in these networks. In this thesis, we propose the Optimal Cell Size (OCS) and the Optimal Channel Assignment (OCA) schemes to address the cell size and packet delay issues for a time division duplex (TDD) wideband code division multiple access (W-CDMA) MCN. OCS finds the optimal cell sizes to provide an optimal balance of cell capacity and coverage to maximize the system throughput, whereas OCA assigns channels optimally in order to minimize packet relaying delay. Like many optimized schemes, OCS and OCA are computationally expensive and may not be suitable for large real-time problems. Hence, we also propose heuristics for solving the problems. For the cell size problem, we propose two heuristics: Smallest Cell Size First (SCSF) and Highest Throughput Cell Size First (HTCSF). For the channel assignment problem, we propose the Minimum Slot Waiting First (MSWF) heuristic. Simulation results show that OCS achieves high throughput compared to that of conventional (single-hop) cellular networks and OCA achieves low packet delay in MCNs. Results also show that the heuristics, SCSF, HTCSF and MSWF, provide good results compared to the optimal ones provided by OCS and OCA, respectively. / Thesis (Ph.D, Computing) -- Queen's University, 2009-02-02 22:53:41.825

Η παρούσα διδακτορική διατριβή πραγματεύεται την ανάλυση και προσομοίωση των συστημάτων απωλειών πολυδιάστατης τηλεπικοινωνιακής κίνησης, σε επίπεδο κλήσεων. Στα πλαίσια της διατριβής έχουν μελετηθεί ασύρματα δίκτυα τεχνολογίας W-CDMA, ενσύρματα συνδεσιμοστρεφή δίκτυα και οπτικά δίκτυα. Ιδιαίτερη έμφαση δόθηκε στα ασύρματα δίκτυα. Η ανάλυση των συστημάτων απωλειών κίνησης εξαρτάται κατά κύριο λόγο από τις διαδικασίες άφιξης και εξυπηρέτησης των κλήσεων. Στην διδακτορική αυτή διατριβή προτείνονται οκτώ νέα μοντέλα απωλειών κλήσεων. Τα έξη από αυτά είναι κατάλληλα για την ανάλυση της απόδοσης σε επίπεδο κλήσεων των ασύρματων δικτύων τεχνολογίας W-CDMA. Τα υπόλοιπα δύο είναι γενικά μοντέλα, κατάλληλα για ενσύρματα συνδεσιμοστρεφή τηλεπικοινωνιακά δίκτυα και οπτικά δίκτυα. Ανάλογα με την διαδικασία άφιξης των κλήσεων στο σύστημα, διακρίνουμε δύο είδη κίνησης: τυχαία και ψευδο-τυχαία. Η τυχαία κίνηση παράγεται όταν η διαδικασία άφιξης των κλήσεων στο σύστημα είναι Poisson. Αυτό αντιστοιχεί στην υπόθεση ότι έχουμε άπειρο πλήθος πηγών που παράγουν κλήσεις. Όταν το πλήθος των πηγών είναι πεπερασμένο, τότε παράγεται ψευδο-τυχαία κίνηση. Ανάλογα με τις απαιτήσεις των κλήσεων σε πόρους και σε χρόνο εξυπηρέτησης κατά την άφιξή τους στο σύστημα, διακρίνουμε τρία είδη κίνησης: σταθερή, ελαστική και προσαρμοζόμενη. Η σταθερή κίνηση παράγεται από κλήσεις που έχουν σταθερές απαιτήσεις σε πόρους και σε χρόνο εξυπηρέτησης. Η ελαστική και η προσαρμοζόμενη κίνηση παράγεται από κλήσεις που μπορούν να έχουν διαφορετικές, εναλλακτικές απαιτήσεις σε πόρους, ανάλογα με την διαθεσιμότητα των πόρων στο σύστημα. Ανάλογα με την συμπεριφορά των κλήσεων μετά την αποδοχή τους στο σύστημα, διακρίνουμε: α) κλήσεις που κατά την διάρκεια της εξυπηρέτησης δεν μπορούν να μεταβάλουν το εύρος ζώνης που τους έχει ανατεθεί (σταθερός ρυθμός μετάδοσης), και β) κλήσεις που κατά την διάρκεια της εξυπηρέτησης μπορούν να μεταβάλουν το εύρος ζώνης (ελαστικός ρυθμός μετάδοσης) προκειμένου το σύστημα να μπορεί να δεχτεί και άλλες κλήσεις. / In this PhD dissertation new multi-rate teletraffic loss models are developed for the call-level analysis of wireless W-CDMA networks, connection-oriented networks and optical networks. The model's accuracy and consistency are verified by simulation and found to be very satisfactory. The analysis of loss systems mainly depends on the call arrival and call service processes. Eight new teletraffic loss models are proposed. Six of them are suitable for the call-level performance analysis of W-CDMA networks, while the other two models are more general and suitable for the analysis of either connection-oriented networks or optical networks. According to the call arrival process, we distinguish two types of traffic: random and quasi-random. Random traffic is generated when the call arrival process is Poisson. This coincides with the assumption that the number of traffic sources is infinite. When the number of traffic sources is finite, we have the so called quasirandom traffic. According to the calls’ resource and service time requirements, we distinguish three types of traffic: stream, elastic and adaptive. Stream traffic is generated by calls that have fixed resource and service time requirements. Elastic and adaptive traffic is generated by calls that may have alternative contingency resource requirements depending on the resource availability or the capacity of the system. According to the calls’ behaviour after their acceptance into the system, we distinguish: a) calls that during their service time are not able to change the number of allocated resources (constant transmission rate) and b) calls that during their service time are able to change the number of allocated resources (elastic transmission rate) in order for the system to be able to accept more calls.

Deployment of antenna arrays is a very promising solution to reduce the Multiple Access Interference (MAI) from high data rate users in the Wideband Code Division Multiple Access (W-CDMA) system. Combining the antenna array with a RAKE receiver, both of which exploits multipath diversity, can significantly improve the system performance. In this research, we investigate the performance of these beamformer-RAKE receivers, also known as two-dimensional (2-D) RAKE receiver, for the reverse link of the W-CDMA system. We consider three different Pilot Symbol Assisted (PSA) beamforming techniques, Direct Matrix Inversion (DMI), Least-Mean Square (LMS) and Recursive Least Square (RLS) adaptive algorithms. Two different Geometrically Based Single Bounce (GBSB) statistical channel models are considered, one, which is more suitable for array processing, and the other is conductive to RAKE combining. The performances of the 2-D RAKE receivers are evaluated in these two channel models as a function of the number of antenna elements and RAKE fingers. It is shown that, in both the cases, the 2-D RAKE receiver outperforms the conventional RAKE receiver and the conventional beamformer by a significant margin. Also, the output SINR expression of a 2-D RAKE receiver with the general optimum beamformer is derived. / Master of Science

<p>Today wireless transmission of data is becoming more and more popular and the need for faster transmission rates is increasing. Since the bandwidth is limited it is important to try to use it to the fullest. CDMA is a technology that allows multiple accesses on the same frequency and time thus making it very bandwidth efficient. The CDMA technology was first introduced in the second generation’s cellular systems but has since then been improved and is reused in today’s 3G systems as Wideband CDMA. ISY is interested in getting a behavioural model of a W-CDMA system since they had developed a DSP processor called BBP1 and were thinking about adding W-CDMA support for it. Even though our system is not implemented on the BBP1 it should provide a good base for future implementations. This thesis project will describe the construction of a behavioural model of a W-CDMA system following the standard specified by 3GPP. The system simulates W-CDMA transmission and reception and has an optional channel used to simulate real world interference. The receiver uses a rake combiner to improve the performance of the system.</p>

Today wireless transmission of data is becoming more and more popular and the need for faster transmission rates is increasing. Since the bandwidth is limited it is important to try to use it to the fullest. CDMA is a technology that allows multiple accesses on the same frequency and time thus making it very bandwidth efficient. The CDMA technology was first introduced in the second generation’s cellular systems but has since then been improved and is reused in today’s 3G systems as Wideband CDMA. ISY is interested in getting a behavioural model of a W-CDMA system since they had developed a DSP processor called BBP1 and were thinking about adding W-CDMA support for it. Even though our system is not implemented on the BBP1 it should provide a good base for future implementations. This thesis project will describe the construction of a behavioural model of a W-CDMA system following the standard specified by 3GPP. The system simulates W-CDMA transmission and reception and has an optional channel used to simulate real world interference. The receiver uses a rake combiner to improve the performance of the system.

Los sistemas MIMO (Multiple-Input Multiple-Output) multi-usuario multi-celda coordinados se definen como una configuración avanzada y cooperativa de sistema MIMO. En estos sistemas, varias estaciones base cooperan perfectamente en datos a través de un enlace de alta capacidad, y transmiten de forma coordinada a todos los usuarios de una determinada área. Además, cada estación base del sistema está sujeta a una restricción en la potencia total que puede transmitir. El objetivo general de la Tesis es estudiar algoritmos que combinan control de potencia y beamforming óptimo para resolver el problema de minimización de potencia en el enlace downlink de un sistema W-CDMA MIMO multi-usuario multi-celda coordinado. Al mismo tiempo, se propone un modelo de sistema matricial y lineal que caracteriza completamente los procesos que tienen lugar en transmisión y en recepción en este tipo de sistemas. Paralelamente, a lo largo de la Tesis se contemplan soluciones a problemas de tipo práctico, como por ejemplo, limitaciones en el tipo de información que se dispone en transmisión. / Botella Mascarell, C. (2008). Algoritmos para Sistemas de Comunicaciones Multi-Usuario con Múltiples Antenas [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/2421 / Palancia