Software defined radio (SDR) introduces endless possibilities for future communication technologies. Instead of being limited to a static segment of the radio spectrum, SDR allows RF front-ends to be more flexible by using digital signal processing (DSP) and cognitive techniques to integrate adaptive hardware with dynamic software. We present the design and implementation of an innovative RF front-end transceiver architecture for application into a SDR test-bed platform. System-level requirements were extracted from the Space Network User Guide (SNUG). Initial system characterization demonstrated image leakage due to poor filtering and mixer isolation issues. Hence, the RF front-end design was re-implemented using the Weaver architecture for improved image rejection performance.

In-phase and quadrature (I/Q) signal generation is often required in modern transceiver architectures, such as direct conversion or low-IF, either for vector modulation and demodulation, negative frequency recovery in direct conversion receivers, or image rejection. If imbalance between the I and Q channels exists, the bit-error-rate (BER) of the transceiver and/or the image rejection ratio (IRR) will quickly deteriorate. Methods for correcting I/Q imbalance are desirable and necessary to improve the performance of quadrature transceiver architectures and modulation schemes. This thesis presents the design and characterization of a monolithic 5-6 GHz Silicon Germanium (SiGe) inductor-capacitor (LC) tank voltage controlled oscillator (VCO) with tunable polyphase outputs. Circuits were designed and fabricated using the Motorola 0.4 ìm CDR1 SiGe BiCMOS process, which has four interconnect metal layers and a thick copper uppermost bump layer for high-quality radio frequency (RF) passives. The VCO design includes full-wave electromagnetic characterization of an electrically symmetric differential inductor and a traditional dual inductor. Differential effective inductance and Q factor are extracted and compared for simulated and measured inductors. At 5.25 GHz, the measured Q factors of the electrically symmetric and dual inductors are 15.4 and 10.4, respectively. The electrically symmetric inductor provides a measured 48% percent improvement in Q factor over the traditional dual inductor. Two VCOs were designed and fabricated; one uses the electrically symmetric inductor in the LC tank circuit while the other uses the dual inductor. Both VCOs are based on an identical cross-coupled, differential pair negative transconductance -GM oscillator topology. Analysis and design considerations of this topology are presented with a particular emphasis on designing for low phase noise and low-power consumption. The fabricated VCO with an electrically symmetric inductor in the tank circuit tunes from 4.19 to 5.45 GHz (26% tuning range) for control voltages from 1.7 to 4.0 V. This circuit consumes 3.81 mA from a 3.3 V supply for the VCO core and 14.1 mA from a 2.5 V supply for the output buffer. The measured phase noise is -115.5 dBc/Hz at a 1 MHz offset and a tank varactor control voltage of 1.0 V. The VCO figure-of-merit (FOM) for the symmetric inductor VCO is -179.2 dBc/Hz, which is within 4 dBc/Hz of the best reported VCO in the 5 GHz frequency regime. The die area including pads for the symmetric inductor VCO is 1 mm x 0.76 mm. In comparison, the dual inductor VCO tunes from 3.50 to 4.58 GHz (27% tuning range) for control voltages from 1.7 to 4.0 V. DC power consumption of this circuit consists of 3.75 mA from a 3.3 V supply for the VCO and 13.3 mA from a 2.5 V supply for the buffer. At 1 MHz from the carrier and a control voltage of 0 V, the dual inductor VCO has a phase noise of -104 dBc/Hz. The advantage of the higher Q symmetric inductor is apparent by comparing the FOM of the two VCO designs at the same varactor control voltage of 0 V. At this tuning voltage, the dual inductor VCO FOM is -166.3 dBc/Hz compared to -175.7 dBc/Hz for the symmetric inductor VCO -- an improvement of about 10 dBc/Hz. The die area including pads for the dual inductor VCO is 1.2 mm x 0.76 mm. In addition to these VCOs, a tunable polyphase filter with integrated input and output buffers was designed and fabricated for a bandwidth of 5.15 to 5.825 GHz. Series tunable capacitors (varactors) provide phase tunability for the quadrature outputs of the polyphase filter. The die area of the tunable polyphase with pads is 920 ìm x 755 ìm. The stand-alone polyphase filter consumes 13.74 mA in the input buffer and 6.29 mA in the two output buffers from a 2.5 V supply. Based on measurements, approximately 15° of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. The output varactor control voltages can be used to achieve a potential ±5° phase flatness bandwidth of 700 MHz. To the author's knowledge, this is the first reported I/Q balance tunable polyphase network. The tunable polyphase filter can be integrated with the VCO designs described above to yield a quadrature VCO with phase tunable outputs. Based on the above designs I/Q tunability can be added to VCO at the expense of about 6 mA. Future work includes testing of a fabricated version of this combined polyphase VCO circuit. / Master of Science