Submitted by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-05-23T17:30:49Z No. of bitstreams: 1 DIS_MAURICIO_TOMAZONI_PEIXOTO_COMPLETO.pdf: 977170 bytes, checksum: 550fe78287feca797929ac42cf3a7c9c (MD5) / Made available in DSpace on 2017-05-23T17:30:49Z (GMT). No. of bitstreams: 1 DIS_MAURICIO_TOMAZONI_PEIXOTO_COMPLETO.pdf: 977170 bytes, checksum: 550fe78287feca797929ac42cf3a7c9c (MD5) Previous issue date: 2016-12-13 / Conselho Nacional de Pesquisa e Desenvolvimento Cient?fico e Tecnol?gico - CNPq / The increasing demand for aesthetic restorations, associated with the evolution of techniques and materials, allowed the preparation of prosthetic pieces of reduced thickness. The introduction of CAD / CAM technology has made accurate and fast restorations. However, the final color of the restoration remains the direct responsibility of the dentist, where a visual assessment of color can cause errors, while an instrumental color measurement has accurate readings. The objective of the study was to investigate the factors that may influence the final color and translucency of different veneers with different thicknesses made by CAD/CAM materials and different types of resin cements on a darkened substrate. The samples were made by copy biogeneric in the CEREC SW 4.2 system, after a sample calculation of the pilot project, 60 upper central incisors of the right side of color C3 of epoxy resin were selected in 12 groups of 5 elements, divided according to type of (Lava Ultimate HT and LT), facet thickness (0.3mm / 0.6mm / 1.0mm) and cement type (Relyx Ultimate and Relyx Veneer). After cementation, the samples were taken with the spectrophotometer at a value of ?E in 6 different times with a silicone guide on the tooth, which ensures that the color is uniform. The results showed a significant difference in the values of ?E in groups 1 and 4 (HT and LT of 0.3 mm) cemented with Relyx Ultimate, in groups 7 and 9 (HT of 0.3 mm and 1.0 mm), and in groups 10 And 12 (LT of 0.3mm and 1.0mm) cemented with Relyx Veneer. However, the results were not significant for the masking of the darkened substrate over time, however, significant differences in ?E values were. / A crescente demanda por restaura??es est?ticas, associada a evolu??o das t?cnicas e materiais, possibilitaram a confec??o de pe?as prot?ticas de espessuras reduzidas. A introdu??o da tecnologia CAD/CAM possibilitou a realiza??o de restaura??es precisas e exatas rapidamente. No entanto, a cor final da restaura??o continua sendo responsabilidade direta do dentista, onde uma avalia??o visual de cor pode ocasionar erros, enquanto uma medi??o de cor instrumental possui leituras precisas. O objetivo do estudo foi realizar uma investiga??o dos fatores que podem influenciar a cor final e translucidez de facetas com diferentes espessuras confeccionadas por materiais CAD/CAM e diferentes tipos de cimentos resinosos sobre um substrato escurecido. As amostras foram confeccionadas por c?pia biogen?rica no sistema CEREC SW 4.2, ap?s c?lculo amostral do projeto piloto, foram selecionados 60 incisivos centrais superiores do lado direito de cor C3 de resina ep?xi foram divididos em 12 grupos de 5 elementos, divididos de acordo com tipo de material (Lava Ultimate HT e LT), espessura da faceta (0,3mm/ 0,6mm/ 1,0mm) e tipo de cimento (Relyx Ultimate e Relyx Veneer). Ap?s a cimenta??o, realizou-se a tomada de cor das amostras com o espectrofot?metro pelo valor de ?E em 6 tempos distintos com uma guia de silicone sobre o dente, que garante que a tomada de cor seja uniforme. Os resultados mostraram diferen?a significativa nos valores de ?E nos grupos 1 e 4 (HT e LT de 0,3mm) cimentados com Relyx Ultimate, nos grupos 7 e 9 (HT de 0,3mm e 1,0mm), e nos grupos 10 e 12 (LT de 0,3mm e 1,0mm) cimentados com Relyx Veneer. Entretanto os resultados n?o foram significativos quanto ao mascaramento do substrato escurecido ao longo do tempo, entretanto, foram observadas diferen?as significativas nos valores de ?E ao longo do tempo em uma an?lise intra-grupos.

With the transistor density on an integrated circuit doubling every 18 months, Moore’s law seems likely to hold for another decade at least. This exponential growth in digital circuits has led to its increased complexity, better performance and is quickly getting less manageable for design engineers. To combat this complexity, CAD tools have been introduced and are still being continuously developed, which prove to be of great help in the digital industry. One of the technologies, that is rapidly evolving as an industry standard, is the Very High Speed Integrated Circuit Hardware Description Language, (VHDL), language. The VHDL standard language along with logic synthesis tools are used to implement complex digital systems in a timely manner. The increase in the number of specialist design consultants, with specific tools accompanied by their own libraries written in VHDL, makes it important for a designer to have an in-depth knowledge about the available synthesis tools and technologies in order to design a system in the most efficient and reliable manner. This research dealt with writing VHDL code in terms of hardware modeling, based on coding styles, in order to get optimum results. Furthermore, it dealt with the interpretation of VHDL code into equivalent optimized hardware implementations, which satisfy the constraints of a set of specifications. In order to obtain a better understanding of the different VHDL tools and their usefulness in different situations, a comparative analysis between Altera’s QuartusII and Xilinx’s ISE Webpack tools, was performed. The analysis compared their Graphics User Interface, VHDL Code Portability and VHDL Synthesis constraints. The analysis was performed by designing and implementing a screensaver circuit on an FPGA and displaying it on the VGA Monitor.

Uppgiften var att ta emot och avkoda en radiosignal för tidsangivelse, DCF77. Avkodaren implementerades i en FPGA-krets från ALTERA. Utvecklingen genomfördes i Quartus II-miljön med språket VHDL samt en alternativ lösning där mjuk processor användes. Både utvecklingsmiljön och språken var väl lämpade för uppgiften. Ett genomgående problem var dock radiomottagaren ofta levererade för svag signal för att kunna avkodas korrekt. Under goda mottagningsförhållanden fungerande dock den beskrivna kretsen tillfredsställande.

<p>In this thesis, a multirate realization of an interpolation operation is explored. As one of the requirements for proper functionality of the digital pulse-width modulator, a 16-bit digital input signal is to be upsampled 32 times. To obtain the required oversampling ratio, five separate interpolator stages were designed and implemented. Each interpolator stage performed uppsampling by a factor of two followed by an image-rejection lowpass FIR filter. Since, each individual interpolator stage upsamples the input signal by a factor of two, interpolation filters were realized as a half-band FIR filters. This kind of linear-phase FIR filters have a nice property of having every other filter coefficient equal to zero except for the middle one which equals 0.5. By utilizing the half-band FIR filters for the actual realization of the interpolation filters, the overall computational complexity was substantially reduced. In addition, several multirate techniques have been utilized for deriving more efficient interpolator structures. Hence, the impulse response of individual interpolator filters was rewritten into its corresponding polyphase form. This further simplifies the interpolator realization. To eliminate multiplication by 0.5 in one of two polyphase subfilters, the filter gain was deliberately increased by a factor of two. Thus, one polyphase path only contained delay elements. In addition, for the realization of filter multipliers, a multiple constant multiplication, (MCM), algorithm was utilized. The idea behind the MCM algorithm, was to perform multiplication operations as a number of addition operations and appropriate input signal shifts. As a result, less hardware was needed for the actual interpolation chain implementation. For the correct functionality of the interpolator chain, scaling coefficients were introduced into the each interpolation stage. This is done in order to reduce the possibility of overflow. For the scaling process, a safe scaling method was used. The actual quantization noise generated by the interpolator chain was also estimated and appropriate system adjustments were performed.</p>

In this thesis, a multirate realization of an interpolation operation is explored. As one of the requirements for proper functionality of the digital pulse-width modulator, a 16-bit digital input signal is to be upsampled 32 times. To obtain the required oversampling ratio, five separate interpolator stages were designed and implemented. Each interpolator stage performed uppsampling by a factor of two followed by an image-rejection lowpass FIR filter. Since, each individual interpolator stage upsamples the input signal by a factor of two, interpolation filters were realized as a half-band FIR filters. This kind of linear-phase FIR filters have a nice property of having every other filter coefficient equal to zero except for the middle one which equals 0.5. By utilizing the half-band FIR filters for the actual realization of the interpolation filters, the overall computational complexity was substantially reduced. In addition, several multirate techniques have been utilized for deriving more efficient interpolator structures. Hence, the impulse response of individual interpolator filters was rewritten into its corresponding polyphase form. This further simplifies the interpolator realization. To eliminate multiplication by 0.5 in one of two polyphase subfilters, the filter gain was deliberately increased by a factor of two. Thus, one polyphase path only contained delay elements. In addition, for the realization of filter multipliers, a multiple constant multiplication, (MCM), algorithm was utilized. The idea behind the MCM algorithm, was to perform multiplication operations as a number of addition operations and appropriate input signal shifts. As a result, less hardware was needed for the actual interpolation chain implementation. For the correct functionality of the interpolator chain, scaling coefficients were introduced into the each interpolation stage. This is done in order to reduce the possibility of overflow. For the scaling process, a safe scaling method was used. The actual quantization noise generated by the interpolator chain was also estimated and appropriate system adjustments were performed.

In this thesis I aim at a design of the laboratory kit and study ways how to programme CPLD devices made by Altera company. The product is used for development and demonstration of applications in CPLD devices made by Altera company. The kit is designed for Altera programming cables and Presto (made by ASIX). Input signals are implemented by a set of switches and buttons on the board. Output states are displayed by LED diods, possibly connected to multiplex the display. The user can connect to external devices via external inputs. Thesis is also aimed at the design PCB of the laboratory kit, subsequent production, recovery and verification of compatibility ALTERA and PRESTO programmers. End of the thesis aims on working with the Quartus II design environment. In particular, it is a guide to working with templates and simulation of VHDL designs.

This work reviews the development frameworks available for the Altera System-On-Chip solutions. These solutions are then compared to solutions available on the Xilinx platform. The RSoC Framework is then presented as an advantageous alternative for the vendor's solutions. This framework is currently available for the Xilinx Zynq platform. Furthermore the work assess the key differences between Xilinx Zynq and Altera Cyclone V SoC platforms and proposes the solution to port the framework to Altera platform. The design and implementation of then RSoC Framework port to Altera Cyclone V SoC is then discussed. Finally the work evaluates the performance of the ported system on the new platform.

There is a belief that radio frequencies  are running out. However, according to a report from the Federal Communications Commission (FCC) in 2002, a different story was told : At any given time and location, much of the prized spectrum lies idle. At the same time, FCC revealed the fact that, in many bands, spectrum access is a more significant problem than physical scarcity of spectrum, in large part due to legacy command-and-control regulation that limits the ability of potential spectrum users to obtain such access. Hence, as opposed to static spectrum access, dynamic spectrum access (DSA) was proposed to solve the predicament. One such DSA model propose the existence of Primary users (licensed users and Secondary users (unlicensed users). Multicarrier communication technology is adopted to enable the coexistence of PU and SU. Orthogonal Frequency Division Multiplexing (OFDM) technology has been popular for multicarrier communications. A disadvantage for OFDM in the Cognitive Radio environment is its large side lobes in the frequency domain, which is a result of single-symbol pulse duration. Filter Bank Multicarrier (FBMC) uses filters that have small side lobes to synthesize/analyze the sub-carriers so as to greatly alleviate the previous mentioned disadvantage. FMT is one FBMC technique.  Although many hardware implementations have been explored during last few decades on OFDM, few FMT hardware implementation results, especially Hardware/Software Co-design, have been presented. This paper presents a HW/SW Co-design implementation result of FMT transceiver on the Altera DE4 board. / Master of Science

No description available.

The security of service, confidential data, and intellectual property are threatened by physical attacks, which usually include reading and tampering the data. In many cases, attackers can have access to the tools and equipment that can be used to read the memory or corrupt it, either by invasive or non-invasive means. The secret keys used by cryptographic algorithms are usually stored in a memory. Physical unclonable functions (PUFs) are promising to deal with such vulnerabilities since, in the case of PUFs, the keys are generated only when required and do not need to be stored on a powered-off chip. PUFs use the inherent variations in the manufacturing process to generate chip-unique output sequences (response) to a query (challenge). These variations are random, device-unique, hard to replicate even by the same manufacturer using identical process, equipment and settings, and supposed to be static, making the PUF an ideal candidate for generation of cryptographic keys. This thesis work focuses on a delay-based PUF called arbiter PUF. It utilizes the intrinsic propagation delay differences of two symmetrical paths. In this work, an arbiter PUF implemented in Altera FPGA has been evaluated. The implementation includes Verilog HDL coding, placement and routing, and the communication methods between PC and FPGAs to make testing more efficient. The experimental results were analyzed based on three criteria, reliability, uniqueness, and uniformity. Experimental results show that the arbiter PUF is reliable with respect to temperature variations, although the bit error rate increases as the temperature difference becomes larger. Results also reveal that the uniqueness of the PUFs on each FPGA device is particularly low but on the other hand, the proportions of different response bits are uniform after symmetric routing is performed. / Tjänstens säkerhet, konfidentiella uppgifter och immateriell egendom hotas av fysiska attacker, som vanligtvis inkluderar läsning och manipulering av uppgifterna. I många fall kan angripare ha tillgång till de verktyg och utrustning som kan användas för att läsa minnet eller skada det , antingen med invasiva eller icke-invasiva medel. De hemliga nycklarna som används av kryptografiska algoritmer lagras vanligtvis i ett minne. Fysiska okonabla funktioner (PUF: er) lovar att hantera sådana sårbarheter eftersom, för PUF: er, nycklarna genereras endast när det behövs och inte behöver lagras på ett avstängd chip. PUF: er använder de inneboende variationerna i tillverkningsprocessen för att generera chip-unika utgångssekvenser (svar) på en fråga (utmaning). Dessa variationer är slumpmässiga, enhetsunika, svårt att kopiera till och med av samma tillverkare med identisk process, utrustning och inställningar, och antas vara statisk, vilket gör PUF till en idealisk kandidat för generering av kryptografiska nycklar. Detta avhandlingsarbete fokuserar på en fördröjningsbaserad PUF som kallas arbiter PUF. Den använder de inneboende utbredningsfördröjningsskillnaderna för två symmetriska vägar. I detta arbete har en arbiter PUF implementerad i Altera FPGA utvärderats. Implementeringen inkluderar Verilog HDLkodning, placering och routing och kommunikationsmetoderna mellan PC och FPGA för att effektivisera testningen. De experimentella resultaten analyserades baserat på tre kriterier, tillförlitlighet, unikhet och enhetlighet. Experimentella resultat visar att arbiter PUF är tillförlitlig med avseende på temperaturvariationer, även om bitfelfrekvensen ökar när temperaturdifferensen blir större. Resultaten avslöjar också att unikheten hos PUF: erna på varje FPGA-enhet är särskilt låg men å andra sidan är proportionerna av olika svarbitar enhetliga efter att symmetrisk dirigering har utförts.