<p>In this thesis, a multirate realization of an interpolation operation is explored. As one of the requirements for proper functionality of the digital pulse-width modulator, a 16-bit digital input signal is to be upsampled 32 times. To obtain the required oversampling ratio, five separate interpolator stages were designed and implemented. Each interpolator stage performed uppsampling by a factor of two followed by an image-rejection lowpass FIR filter. Since, each individual interpolator stage upsamples the input signal by a factor of two, interpolation filters were realized as a half-band FIR filters. This kind of linear-phase FIR filters have a nice property of having every other filter coefficient equal to zero except for the middle one which equals 0.5. By utilizing the half-band FIR filters for the actual realization of the interpolation filters, the overall computational complexity was substantially reduced. In addition, several multirate techniques have been utilized for deriving more efficient interpolator structures. Hence, the impulse response of individual interpolator filters was rewritten into its corresponding polyphase form. This further simplifies the interpolator realization. To eliminate multiplication by 0.5 in one of two polyphase subfilters, the filter gain was deliberately increased by a factor of two. Thus, one polyphase path only contained delay elements. In addition, for the realization of filter multipliers, a multiple constant multiplication, (MCM), algorithm was utilized. The idea behind the MCM algorithm, was to perform multiplication operations as a number of addition operations and appropriate input signal shifts. As a result, less hardware was needed for the actual interpolation chain implementation. For the correct functionality of the interpolator chain, scaling coefficients were introduced into the each interpolation stage. This is done in order to reduce the possibility of overflow. For the scaling process, a safe scaling method was used. The actual quantization noise generated by the interpolator chain was also estimated and appropriate system adjustments were performed.</p>

In this thesis, a multirate realization of an interpolation operation is explored. As one of the requirements for proper functionality of the digital pulse-width modulator, a 16-bit digital input signal is to be upsampled 32 times. To obtain the required oversampling ratio, five separate interpolator stages were designed and implemented. Each interpolator stage performed uppsampling by a factor of two followed by an image-rejection lowpass FIR filter. Since, each individual interpolator stage upsamples the input signal by a factor of two, interpolation filters were realized as a half-band FIR filters. This kind of linear-phase FIR filters have a nice property of having every other filter coefficient equal to zero except for the middle one which equals 0.5. By utilizing the half-band FIR filters for the actual realization of the interpolation filters, the overall computational complexity was substantially reduced. In addition, several multirate techniques have been utilized for deriving more efficient interpolator structures. Hence, the impulse response of individual interpolator filters was rewritten into its corresponding polyphase form. This further simplifies the interpolator realization. To eliminate multiplication by 0.5 in one of two polyphase subfilters, the filter gain was deliberately increased by a factor of two. Thus, one polyphase path only contained delay elements. In addition, for the realization of filter multipliers, a multiple constant multiplication, (MCM), algorithm was utilized. The idea behind the MCM algorithm, was to perform multiplication operations as a number of addition operations and appropriate input signal shifts. As a result, less hardware was needed for the actual interpolation chain implementation. For the correct functionality of the interpolator chain, scaling coefficients were introduced into the each interpolation stage. This is done in order to reduce the possibility of overflow. For the scaling process, a safe scaling method was used. The actual quantization noise generated by the interpolator chain was also estimated and appropriate system adjustments were performed.

A multi-precision function interpolator, which is fitted in with the IEEE-754 single precision floating point standard, is proposed in this paper. It provides logarithms, exponentials, reciprocal and square root reciprocal operations. Each operation is able to dynamically select four different precision modes in demand. The hardware architecture is designed with fully pipeline in order to comply with hardware architectures of general digital signal processors (DSPs) and graphics processors (GPUs). When considering the usefulness of each precision mode, it is designed to minimize the error among various modes as far as possible in the beginning. According to the precision from high to low, function interpolator can provide 23, 18, 13 and 8-bit accuracy respectively in spite of the rounding effect. This function interpolator is designed based on the look-up table method. It can get the approximation value of target function through the calculation of quadratic polynomial. The coefficient of quadratic polynomial is obtained by piecewise minimax approximation. Before implementing the hardware, we use the Maple algebra software to generate the quadratic polynomial coefficients of aforementioned four operations, and estimate whether these coefficients can meet IEEE-754 single precision floating point standard. In addition, we take the exhaustive search to check the results generated by our implementation to make sure that it can meet the requirements for various operations and precision modes. When performing one of the above four operations, only the tables of the operation are used to obtain the quadratic polynomial coefficient. Therefore, we can take the advantage of the tri-state buffer as a switch to reduce dynamic power consumption of tables for the other three operations. In addition, when performing lower precision modes, we can turn off a part of hardwares, which are used to calculate the quadratic polynomial, to save the power consumption more effectively. By providing multi-precision hardware, we hope users or developers, those who use the battery device, can choose a lower precision mode within the permissible error range to extend the battery life.

For the next generation of multimedia applications such as digital video broadcasting, multimedia message service and video conference, enormous amounts of video context will be transmitted and exchanged through the wireless channel. Due to the limited communication bandwidth, how to achieve more efficient, reliable, and robust video compression is a very important issue. H.264/AVC (Advanced Video Coding) is one of the latest video coding standards, which is anticipated to be adopted in many future application systems due to its excellent compression efficiency. In this thesis, the implementation issue of the H.264 decoding algorithm on the SOC (System-On-Chip) development platform is addressed. Several key modules of H.264 decoders including color space converter, inter-interpolation, transformation rescale modules are all realized by dedicated hardware architectures. A novel low-cost fast scalable deblocking filter based on single-port memory architecture is also proposed which can support fast real-time deblocking filtering process. The entire H.264 decoder system is prototyped on the Altera SOPC platform, and the decoding result is displayed directly on the monitor. All the hardware modules are hooked on the system Avalon bus, and interact with Altera NIOS-¢º processor. Through the hardware/software co-design approach, the decoding speed can be increase by a factor of 1.9.

My task was to build a smaller structure triaxial CNC milling. I designed electronics for motion control. The main part is the implementation of the control unit, which will provide control of the machine. The work includes the complete design, PCB design and program description for the uP ARM. The unit can work independently as well as hardware interpolator connected to the PC.

The dissertation investigates the issues of analyzing a digital Sigma-Delta digital-to-analog converter (DAC) for audio power amplifiers. The main objects of research include a digital Sigma-Delta audio power DAC, improvement of its structure and an experimental research. The primary purpose of the dissertation is to suggest methods for improvement the structure of digital Sigma-Delta audio power DAC interpolator and the converter analysis. / Disertacijoje nagrinėjami Sigma-Delta skaitmeniniai-analoginiai (skaičiaus-analogo, SA) keitikliai garso galios stiprintuvams. Pagrindinis tyrimų objektas – skaitmeninis Sigma-Delta garso galios SA keitiklis, jo sandaros tobulinamas bei eksperimentinis tyrimas. Disertacijos tikslas – pasiūlyti skaitmeninio Sigma-Delta garso galios SA keitiklio interpoliatoriaus struktūros tobulinimo bei keitiklio tyrimo metodus.

No description available.

The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integrator and a switched-capacitor resistor. Since the input to output of the FBVCO has a low-pass characteristic, any disturbance on the control voltage should be filtered and cannot affect the output phase. We are able to reduce the output frequency variation approximately 75% compared to the conventional PLL when the radiation pulse strikes on the control voltage. The proposed RHBD PLL is implemented in 130 nm and consumes 6.2 mW at 400 MHz operating frequency. Thirdly, a novel adaptive-bandwidth PLL is illustrated to optimize the jitter performance in a wide operating frequency range. We achieve a constant ratio of bandwidth and reference frequency with a closed loop VCO and an overdamping system with a charge pump (CP) current proportional to the VCO frequency for the adaptive-bandwidth technique. The proposed adaptive-bandwidth PLL presents 0.6% RMS jitter over the entire frequency range from 320 MHz to 2.56 GHz, which is 70% smaller than the conventional fixed-bandwidth PLL. Finally, we have developed a new feedback DCO to achieve a linear gain of DCO so that the DPLL can provide stability and a wide operating range in different process variations. Due to the negative feedback loop of the proposed DCO, the feedback DCO presents a linear gain from an input digital word to an output frequency. Moreover, we can control the bandwidth of the feedback DCO to optimize the total output phase noise in DPLL. In simulation, we can obtain 17 MHz/LSB of the peak-to-peak gain of the feedback DCO, which is reduced 96% over the conventional DCO.

No description available.

[pt] Esta pesquisa de mestrado tem por objetivo avaliar a confiabilidade metrológica de sensores eletrolíticos (eletroníveis) utilizados para determinar desvios angulares de elementos de estruturas de engenharia civil. A motivação pelo trabalho decorreu da percepção de que usuários de eletroníveis nem sempre consideram a importância do processo de calibração e das incertezas que lhe são associadas na confiabilidade de suas medições. A metodologia utilizada consistiu em avaliar, com o rigor metrológico, um processo de calibração de conjuntos de eletroníveis montados em uma barra rígida, porém pivotada em uma de suas extremidades assim permitindo deslocamentos angulares. O resultado das análises de dados de quatro calibrações típicas de um conjunto de 36 eletroníveis, agrupados de nove em nove, permitiu mostrar que a expressão das incertezas associadas à medição constitui-se em fundamento essencial para assegurar a confiabilidade metrológica dos eletroníveis, assim validando um método de descarte de eletroníveis fora da tolerância admissível para uma determinada aplicação em engenharia. Dentre as conclusões do trabalho foi possível qualificar o tratamento estatístico dos níveis de incerteza como uma estratégia suficientemente robusta para validar o eletronível como instrumento fidedigno para medição de ângulo com um nível de confiança adequado à sua aplicação em engenharia civil. / [en] This master s research aims to evaluate the metrological reliability of electrolytic tilt sensors (electrolevels) used to determine angular deviations of components of civil engineering structures. The motivation for the work arises from the perception that users of electronic devices do not necessarily consider the importance of the calibration process and the uncertainties that are associated to it in the reliability of their measurements. The methodology used consisted in evaluating, with the metrological rigor, a process of calibration of sets of eletronics mounted on a rigid bar, but pivoted at one of its ends thus allowing angular displacements. The result of the data analyzes of four typical calibrations of a set of 36 electrolevels, grouped in four batches of nine sensors each, allowed to show that the expression of the uncertainties associated with the measurement constitutes an essential fundament to assure the metrological reliability of the electrolevels, therefore validating a method of disposal of electrolevels outside the permissible tolerance for a given engineering application. Among the conclusions of the study, it was possible to qualify the statistical treatment of the levels of uncertainty as a sufficiently robust strategy to validate the electrolevel as a reliable instrument for angle measurement with a level of confidence appropriate to its application in civil engineering.