The emphasis on higher data rates, spectral efficiency and cost reduction has driven the field towards linear modulation techniques such as quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), wideband code division multiple access (WCDMA), and orthogonal frequency division multiplexing (OFDM). The result is a complex signal with a non-constant envelope and a high peak-to-average power ratio. This characteristic makes these signals particularly sensitive to the intrinsic nonlinearity of the RF power amplifier (PA) in the transmitter. The nonlinearity will generate intermodulation (IMD) components, also referred to as out-of-band emission or spectral re-growth, which interfere with adjacent channels. Such distortion, or so called Adjacent Channel Interference (ACI), is strictly limited by FCC and ETSI regulations. Meanwhile, the nonlinearity also causes in-band distortion which degrades the bit error rate performance. Typically, the required linearity can be achieved either by reducing power efficiency or by using linearization techniques. For a Class-A PA, simply “backing off” the input power level can improve linearity; however, for high peak to average power ration (PAPR) signals, this normally reduces the power efficiency down to 10% while increasing heat dissipation up to 90%.When considering the vast number of base stations that wireless operators need to account for, increasing power consumption, or in other words, power back-off is not a viable tradeoff. Therefore, amplifier linearization has become an important technology and a desirable alternative to backing-off an amplifier in modern communications systems. In this work, a novel adaptive algorithm is presented for predistorter linearization of power amplifiers. This algorithm uses Pade-Chebyshev polynomials and a QR decomposition followed by back substitution to find the pre-distorter coefficients.This algorithm is implemented on a Field Programmable Gate Array (Stratix 1S80).The implementation provides improved linearization and also runs the algorithm fast enough so that the adaptive part can be done quickly. Yet another challenge was the integration of a transmitter, receiver and this adaptive algorithm into a single FPGA chip and its communication with a base station. The work thus presents a novel pre-distortion implementation technique using an FPGA and a soft processor (Nios 2) which provides significant intermodulation distortion suppression.

The need for high spectral efficiency and data rate drives the modulation schemes like OFDM and QAM. The resulting signal is a complex signal with high peak to average power ratio. This property causes signal sensitivity to the non-linearity of power amplifiers. Power amplifiers create out-of-band distortion, in band distortion and spectral re-growth. The spectral re-growth affects the adjacent channels and cause Adjacent Channel Interference (ACI). So linearization techniques should be used to remove the skirts produced by the amplifier in the adjacent frequencies. The objective of this thesis is to figure out a pre distortion method that is simple enough to implement with an analog circuit. We are proposing a novel method to model the non linearity and use the same model as post-distorter and pre-distorter to invert non linearity so linear gain is maintained. The implementation is generic to all the non linear systems and can be implemented to invert the non linearity of any such system.

This thesis presents the design and development of two switching amplifiers used to drive the so-called smart material actuators. Different from conventional circuits, a smart material actuator is ordinarily a highly capacitive load. Its capacitance is non-linear and its strain is hysteretic with respect to its electrical control signal. This actuator's reactive load property usually causes a large portion of reactive power circulating between the power amplifier and the driven actuator, thus reduces the circuit efficiency in a linear power amplifier scenario. In this thesis, a switching amplifier design based on the PWM technique is proposed to develop a highly efficient power amplifier, and peak current mode control is proposed to reduce the actuator's hysteretic behavior. Since the low frequency current loop gain tends to be low due to the circuit's capacitive load, average current mode control is further proposed to boost the low frequency current loop gain and improve the amplifier's low frequency performance. Both of the circuits have been verified by prototype design and their experimental measurement results are given. / Master of Science

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The demand for low-power A/D conversion techniques has motivated the exploration of charge-transfer amplifiers (CTAs) to construct efficient, precise voltage comparators. Despite notable advantages over classical, continuous-time architectures, little is understood about the dynamic behavior of CTAs or their utility in precision A/D converters. Accordingly, this dissertation presents several advancements related to the design and analysis of charge-transfer amplifiers for low-power data conversion. First, an analysis methodology is proposed which leads to a deterministic model of the voltage transfer function. The model is generalized to any timing scheme and can be extended to account for nonlinear threshold modulation. The model is compared with simulation results and test chip measurements, and shows good agreement over a broad range of circuit parameters. Three new charge-transfer amplifier architectures are proposed to address the limitations of existing designs: first, a truly differential CTA which improves upon the pseudo-differential configuration; second, a CTA which achieves more than 10x reduction in input capacitance with a moderate reduction in common mode range; third, a CTA which combines elements of the first two but also operates without a precharge voltage and achieves nearly rail to rail input range. Results from test chips fabricated in 0.6 um CMOS are described. Power dissipation in CTAs is considered and an idealized power consumption model is compared with measured test chip results. Four figures of merit (FOMs) are also proposed, incorporating power dissipation, active area, input charging energy and accuracy. The FOMs are used to compare the relative benefits and costs of particular charge-transfer amplifiers with respect to flash A/D converter applications. The first 10-bit CTA-based A/D converter is reported. It consumes low dynamic power of 600 uW/MSPS from a 2.1 V supply, 40% less than the current state of the art of 1 mW/MSPS. This subranging type converter incorporates capacitive interpolation to achieve a nearly ideal comparator count and power consumption. A distributed sample-and-hold (S/H) eliminates the need for a separate S/H amplifier. A test chip, fabricated in 0.6 um 2P/3M CMOS, occupies 2.7 mm2 and exhibits 8.2 effective bits at 2 MSPS.

This dissertation discusses and compares the existing compensation methods for operational amplifiers. It explores a method to stabilize the op amps without sacrificing bandwidth to the same degree that commonly used methods do. A creative design methodology combining intuition, mathematical analysis, and mixed level simulation is explored for the new compensation scheme. The mixed level approach, associating system level simulation for most circuits along with device level simulation for some critical analog circuit paths, is presented to verify the behavior of new design concepts in an effective way. This approach also provides sufficient accuracy to predict the circuit performance realistically. The new feedforward compensation method overcomes the serious drawback of the widely used pole splitting method, which greatly narrows the bandwidth. It can improve the phase margin as well as optimize the bandwidth of the op amp. The proposed feedforward compensation method can be easily applied to the popular two gain stage op amp architectures with very little alteration. MOS devices are used in the weak inversion region or the subthreshold inversion region to minimize dc source power. A feasible configuration for high gain, low power op amp design utilizing subthreshold operation along with active operation is proposed. This op amp uses composite cascode connections for the differential input stage, a common source second stage, and a current mirror. A prototype of the op amp was fabricated in a 0.25 µm CMOS process. The proposed op amp produces an open loop gain above one million with low power consumption around 110 µW and shows a favorable slew rate and GBW product compared to other amplifiers driving large capacitive loads. In addition, the composite cascode amplifier requires a compensation capacitor of only 3.5 pF which allows a very small op amp cell. This design is intended for applications where simplicity of layout, small cell size, and low power are important. The open loop gain of this design is comparable to bipolar op amps and exceeds all known reported CMOS designs using the classic Widlar architecture. The fabricated op amp test results show that the BSIM3 model in CADENCE Spectre Spice Simulation matches closely to the experimental results in spite of the low current weak inversion operation of the composite cascode output device and thus provide confidence in the simulation for other similar designs. While facing the challenge of measuring the op amp open loop characteristics at decreased power supply voltages, a few viable techniques were developed to measure the op amp open loop parameters using typically available bench test equipment.

This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are discussed and developed. These techniques are used to design four fully-differential rail-to-rail amplifiers. The highest gain is shown to be attained using a drain voltage equalization (DVE) or active-bootstrapping technique which produces more than 100dB of gain in a two stage amplifier with a bulk-driven input pair while showing no bandwidth degradation when compared to amplifier architectures with similar biasing. The low voltage design techniques are extended to switching and sampling circuits. A 10-bit digital to analog converter (DAC) and a 10-bit analog to digital converter (ADC) are designed and fabricated in a 0.35um dual-well CMOS process to prove the developed design methods, architectures, and techniques. The 10-bit DAC operates at 1MSPS with near rail-to-rail differential output operation with a 700mV supply voltage. This supply voltage, which is 150mV lower than the VT+2Vds,sat limit, is attained by using a bulk driven threshold voltage lowering technique. The ADC design is a fully-differential pipelined 10-bit converter that operates at 500kSPS with a full scale input range equal to the supply voltage and can operate at supply voltages as low as 650mV, 200mV below the VT + 2Vds,sat limit. The design methods and architectures can be used in advanced processes to maintain gain and minimize supply voltage. These designs show a minimum supply improvement over previously published designs and prove the efficacy of the design architectures and techniques presented in this dissertation.

Electrochemical measurements are utilized in various fields, including healthcare (e.g., potentiometric measurements for electrolytes in blood and blood gas, amperometric biosensing of glucose as in blood glucose meters), water quality (e.g., pH measurement, voltammetric analyses for heavy metals), and energy. Much of the appeal of electrochemical analyses can be attributed to the relative simplicity, low cost and lack of maintenance associated with electrochemical instruments, along with techniques that can exhibit high sensitivity and selectivity, wide linear dynamic range, and low limits of detection for many analytes. While commercial electrochemical analyzers are less expensive than many other instruments for chemical analyses and are available from various manufacturers, versatility and performance often coincide with added expense. Recently, the development of low-cost, adaptable, open-source chemical instruments, including electrochemical analyzers, has emerged as a topic of great interest in the scientific community. In contrast to commercial instruments, for which schematics and underlying operation details are often obscured – severely limiting modifications and improvements, creators of open-source instruments release all the necessary information for reproduction of the hardware and software. As a result, open-source instruments not only serve as excellent teaching tools for novices to gain experience in electronics and programming, but also present opportunity to design and develop low-cost, portable instruments, which have particular significance for point-of-care sensing applications, use in resource-limited settings, and the rapidly developing field of on-body sensors. In this work, we report the design of a low-cost, compact electrochemical analyzer based on an open-source Arduino microcontroller. The instrument is capable of performing electrochemical analyses such as cyclic and linear sweep voltammetry with an operating range of ± 138 ��A and ± 1.65 V. Performance of the platform is investigated with low-cost pencil graphite electrodes and results compared to commercial potentiostats.

Interest in Raman amplification has undergone a revival due to the rapidly increasing bandwidth requirements for communications transmission, both for long haul and local area networks, and recent developments in the telecom fiber industry and diode laser technology. In contrast to rare earth doped fiber amplifiers, for which the range of wavelengths is fixed and limited, Raman gain bandwidths are larger and the operating wavelength is fixed only by the pump wavelength and the bandwidth of the Raman active medium. In this context, glasses are the material of choice for this application due to their relatively broad spectral response, and ability of making them into optical fiber. This dissertation summarizes findings on different oxide-based glasses that have been synthesized and characterized for their potential application as Raman gain media. Two main glass families were investigated: phosphate-based glass matrices for broadband Raman gain application and TeO2-based glasses for high Raman gain amplification. A phosphate network was preferred for the broadband application since the phosphate Raman active modes can provide amplification above 1000 cm-1, whilst TeO2-based glasses were selected for the high gain application due to their enhanced nonlinearities and polarizabilities among the other oxide-based network formers. The results summarized in this dissertation show that phosphate-based glasses can provide Raman amplification bandwidths of up to 40 THz, an improvement of almost 5 times the bandwidth of SiO2. On the other hand, tellurite-based glasses appear to be promising candidates for high gain discrete Raman applications, providing peak Raman gain coefficients of up to 50 times higher than SiO2, at 1064 nm. Although, visible spontaneous Raman scattering cross-section measurement is the most frequently used tool for estimating the strength and spectral distribution of Raman gain in materials, especially glasses, there are some issues that one needs to be aware when conducting these measurements near the absorption band edge of the material. This led to the detection of an inherent frequency-dispersion in the Raman susceptibility and a resonant enhancement phenomenon when measurements were conducted near the absorption edge of the material.

This thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the HCE phenomenon is one of the serious reliability issues in the aggressively scaled RF CMOS design, especially for long-term operation of these devices. The predicted degradation from simulation results can be used design reliable CMOS RF circuits.