Millimeter wave (mm-Wave) has become increasingly popular frequency band for next-generation high-speed wireless communications. In mm-Wave, the wireless channel path loss is severe, demanding a high output power in transmitters (Tx) to meet a required SNR in receivers (Rx). Due to the intractable speed-power tradeoff ingrained in silicon processes, however, achieving a high power at mm-Wave, particularly over W-band (> 90 GHz), is challenging in silicon power amplifiers. To relieve the output power burden, phased-arrays are widely adopted in mm-Wave wireless communication systems -- namely, by leveraging a parallel power combining in the space domain, inherent in the phased arrays, the required output power per array element can be reduced significantly with increasing array size. In large arrays ( > 100's -- 1000's number of arrays), the required output power per element could be small, typically around several 10's mW or less in silicon-based phased arrays. In such small-to-medium scale output power level, the static power dissipations by transistor knee voltage and passive components could be a significant portion of the output power, decreasing power efficiency of power amplifiers drastically. This poses a significant concern on the power efficiency of the large-scale silicon-based phased arrays in mm-Wave. Another critical problem in mm-Wave wireless systems design is the increase of passive reactive components loss caused by worsening skin depth effect and increasing dielectric loss through silicon substrate. This essentially degrades the reactive components quality factor (Q) and limits frequency selectivity of the silicon-based mm-Wave systems. This thesis tackles these two major technical challenges to provide high frequency selectivity with maintaining high power efficiency for future mm-Wave wireless systems over W-band and beyond. First, various high-efficiency techniques such as impedance tuning with a reactive component at a cascoding stage in conventional stacked power amplifiers or load-pull based inter-stage matching technique, rather than conventional conjugate matching, have been applied to W-band CMOS and SiGe BiCMOS amplifiers to improve power efficiency with 5-10 dBm output power level, suitable for a large phased array applications, as detailed in Chapter 2 and 3. Second, a 4-tap finite impulse response (FIR) filter based receiver architecture is presented in Chapter 4. The FIR filtered receiver leverages a sinc-pulse type frequency nulls built-in in the transmission-line based FIR filter's frequency response to increase frequency selectivity. The proposed FIR filtered receiver achieves > 40-dB image rejection by placing an image signal at the null frequency at D-band, one of the largest image rejection performance at the highest frequency band reported so far. / Ph. D. / Due to recent advances in Silicon based solid-state technologies, the interest towards the millimeter wave (mm-Wave) frequency band has been emerging for next-generation high-speed wireless communication applications. One of the most significant parameters in a communication system would be the output power of a transmitter. However, the output power is limited especially at mm-wave frequencies. A phased array is one of the viable solutions to overcome this burden by utilizing a parallel power combing in the space domain. The required output power per element can be relieved, typically around several tens of mill watts or less. There are two major factors limiting the output power, which are the high loss of passive and active devices. This dissertation presents solutions to overcome these challenges. In addition, a 4-tap finite impulse response (FIR) filter based receiver architecture is introduced, which rejects unwanted image signals in heterodyne systems by utilizing sinc-pulse type frequency nulls. The proposed FIR filter achieves more than 40 dB of image rejection at D-band (110-170 GHz), which is one of the highest filtering performance in the millimeter-wave frequency band.

Detta arbete syftar till att identifiera och undersöka metoder för att designa och optimera transistorer i effektförstärkare av typen A, AB, B och F utifrån parametrar som linjäritet, arbetsfrekvens, uteffekt och verkningsgrad. Arbetsfrekvensen ska vara 1 GHz och effektförstärkaren ska ha hög linjäritet samt verkningsgrad. Det resultat som förväntas efter avslutat arbete är en optimeringsteknik som steg för steg kan användas i simulerad miljö för att optimera transistorer i effektförstärkare. En grundtopologi för alla effektförstärkare konstrueras och endast en transistor används vid design av effektförstärkarna. Olika metoder undersöks för att optimera förstärkarna. De metoder som används vid optimering av effektförstärkarna är två typer av Loadpull-analys, spänning och strömkvot, DCIV-karaktäristik och stabilitetsanalys. Dessa metoder används och demonstreras i arbetet. En optimerad förstärkare av varje förstärkarklass presenteras. De metoder som används evalueras och en optimeringsteknik presenteras. / This work aims to design and optimize transistors in power amplifiers of types A, B, AB, and F based on parameters such as linearity, operating frequency, output power and efficiency. The operating frequency is set to 1 GHz, and the power amplifier shall have high linearity and high efficiency. The expected result after completing the work is an optimization technique that can be used step by step in a simulated environment to optimize transistors in power amplifiers. A basic topology, for all power amplifiers which were analysed, is constructed and only one transistor is used in the design of the power amplifiers. Various methods are investigated to optimize the amplifiers. The methods used in the optimization of the power amplifiers are two types of Loadpull-analysis, voltage and current ratio, DCIV-characteristics and stability analysis. These methods are used and demonstrated in the work. Optimized amplifiers of the different amplifier classes are presented. The methods used has been evaluated and an optimization technique is presented.

Circuits to extend operation data-rate of a optical receiver is investigated in the dissertation. A new input-stage topology for a transimpedance amplifier (TIA) is designed to achieve 50% higher data-rate is presented, and a new architecture for clock recovery is proposed for 50% higher clock rate. The TIA is based on a gm-boosted common-gate amplifier. The input-resistance is reduced by modifying a transistor at input stage to be diode-connected, and therefore lowers R-C time constant at the input and yielding higher input pole frequency. It also allows removal of input inductor, which reduces design complexity. The proposed circuit was designed and fabricated in 32 nm CMOS SOI technology. Compared to TIAs which mostly operates at 50 GHz bandwidth or lower, the presented TIA stage achieves bandwidth of 74 GHz and gain of 37 dBohms while dissipating 16.5 mW under 1.5V supply voltage. For the clock recovery circuit, a phase-locked loop is designed consisting of a frequency doubling mechanism, a mixer-based phase detector and a 40 GHz voltage-controlled oscillator. The proposed frequency doubling mechanism is an all-analog architecture instead of the conventional digital XOR gate approach. This approach realizes clock-rate of 40 GHz, which is at least 50% higher than other circuits with mixer-based phase detector. Implemented with 0.13-μm CMOS technology, the clock recovery circuit presents peak-to-peak clock jitter of 2.38 ps while consuming 112 mW from a 1.8 V supply. / Ph. D. / This dissertation presents two electronic circuits for future high-speed fiber optics applications. A receiver in a optical communication systems includes several circuit blocks serving various functions: (1) a photodiode for detecting the input signal; (2) a transimpedance amplifier (TIA) to amplify the input signal; (3) a clock and data recovery block to re-condition the input signal; and (4) digital signal processing. High speed integrated circuits are commonly fabricated in SiGe or other high electron mobility semiconductor technologies, but receiver circuits based on Silicon using complementary metal oxide semiconductor (CMOS) technology has gained attention in open literatures due to its advantage of integrating signal processing . This dissertation shows a TIA circuit and a clock recovery circuit designed and implemented in CMOS technology. The TIA circuit is based on a ”g_m-boosted common-gate amplifier” topology, and a slight modification at the input of the topology is proposed. Implemented in 32nm SOI CMOS technology, the TIA measures bandwidth that achieved 100 Gb/s bandwidth. The bandwidth is increased by at least 48% when compared with state-of-the-art CMOS TIA’s. The clock recovery circuit is a phase-locked loop with a mixer as the phase detector. An architectural change of replacing the conventional frequency doubling mechanism is proposed. The circuit is implemented in 0.13 µm CMOS technology, and it achieved 40 GHz clock rate with 40 Gb/s data input, which is about 40% increase of clock rate compared to state-of-the-art clock recovery circuits of similar architecture.

As complimentary metal-oxide semiconductor (CMOS) technologies scale and field-effect transistor (FET) architectures change, the factors in deciding to utilize analog or digital transistor behaviors evolve. This thesis examines three case studies where traditionally analog or digital circuitry has dominated published works but I show that the opposite regime has significant benefits in scaled CMOS technologies. I present a highly digital operational amplifier (traditionally analog) and two artificial neurons (traditionally digital). In Chapters 2 and 3 I present a highly-digital five-stage zero-crossing-based amplifier which breaks the trade-off between slew rate and settling accuracy. I investigate the optimal charge pump design by analyzing the effects of the current scaling factor, number of current sources, maximum current value, and input amplitude on the settling performance including overshoot and settling time. I find that there exists an optimal number of stages that yields the fastest settling for a given total current and load capacitance. The proposed amplifier achieves a signal-to-noise ratio of 57 dB at a sampling rate of 40 MHz and consumes 1.45 mW under a 1V supply. In Chapters 4 and 5, I propose two novel analog artificial spiking neurons, operating in the voltage domain and phase domain respectively. The voltage domain neuron presented in Chapter 4 implements a novel fine-tuning method called neuromodulatory tuning which reduced the number of parameters to be tuned by four orders of magnitude as compared with traditional fine-tuning methods. Chapter 5 presents the design of a novel phase-domain neuron. Voltage domain neurons mimic biological neurons by integrating charge on a capacitor. I instead integrate phase in a voltage-controlled ring oscillator (VCO). I also propose a novel bidirectional switched-capacitor synapse which saves significant area compared to bidirectional current based synapses. The proposed neuron, synapse and weight memory occupy only 21x27um, and consume 134fJ/spike under a 0.35V supply.

Yes / Fourth generation systems require the use of both amplitude and phase modulation to efficiently utilize the available spectrum and to obtain high data rates, hence imposing stringent requirements on the power amplifier in terms of efficiency and linearity and requires the power amplifier to operate linearly and efficiently. The B3G base station transceiver Doherty power amplifier was designed to operate over the frequency range of 3.47GHz to 3.53GHz mobile WiMAX band using Freescale¿s N-Channel Enhancement-Mode Lateral MOSFET Transistor, MRF7S38010HR3; The performances of the Doherty amplifier are compared with that of the conventional Class AB amplifier. The results of 43 dBm output power and 66% power added efficiency are achieved.

Yes / Much attention has been paid to making 5G developments more en-ergy efficient, especially in view of the need for using high data rates with more complex modulation schemes within a limited bandwidth. The concept of the Doherty power amplifier for improving amplifier efficiency is explained in addi-tion to a case study of a 70W asymmetrical Doherty power Amplifier using two GaN HEMTs transistors with peak power ratings of 45W and 25W. The rationale for this choice of power ratio is discussed. The designed circuit works in the 3.4GHz frequency band with 200 MHz bandwidth. Rogers RO4350B substrate with dielectric constant εr=4.66 and thickness 0.035 mm is used. The perfor-mance analysis of the Doherty power amplifier is simulated using AWR MWO software. The simulated results showed that 54-64% drain efficiency has been achieved at 8 dB back-off within the specified bandwidth with an average gain of 10.7 dB.

Les systèmes embarqués tels que les téléphones portables ou les lecteurs multimédia intègrent de plus en plus de fonctions consommatrices d'énergie ce qui a pour conséquence directe une diminution de leurs autonomies. Les applications audio dans les téléphones cellulaires et en particulier l'application casque font partie des fonctions les plus consommatrices d'énergie. Après un état de l'art des solutions permettant l'amplification de signaux audio, l'amplificateur de classe G à été identifié comme étant le meilleur candidat pour obtenir une amélioration du rendement tout en fournissant une bonne qualité de reproduction sonore. Nos travaux se sont plus particulièrement focalisés sur la détection d'enveloppe de ces architectures qui est un facteur clé dans la maximisation du rendement. Une étude des propriétés temporelles, fréquentielles et statistiques des signaux présents en entrée de l'amplificateur a ainsi été menée pour mettre en évidence les différences entre les signaux classiquement utilisés (signal sinusoïdal) et les signaux réellement écoutés par les utilisateurs (musique). Après avoir effectué une sélection de signaux pour la suite de notre étude, nous avons également caractérisé la puissance correspondant à des conditions normales d'écoute afin d'obtenir par la suite un environnement de test proche des conditions réelles de fonctionnement. Un modèle simplifié et rapide d'amplificateur hybride permettant d'obtenir en quelques dizaines de secondes, l'évaluation du rendement, de la consommation et de la qualité sonore dans des conditions réelles de fonctionnement a été développé. Notre modèle, entièrement configurable et réadaptable à d'autres types de circuits a été validé par mesures pratiques des performances d'un amplificateur existant. Les paramètres de la détection d'enveloppe de ce modèle ont fait l'objet d'une optimisation basée sur le couplage séquentiel de deux algorithmes d'optimisation, permettant ainsi dans un temps limité d'obtenir une solution optimale sans solution de départ sous des conditions réelles d'utilisation. La suite de notre étude nous a conduit à étudier, modéliser, optimiser et comparer des amplificateurs de classe G possédant un nombre de tensions d'alimentation supérieur (3, 4) ainsi que des amplificateurs de classe H (alimentations continues) afin d'améliorer encore le rendement. Enfin, nous avons proposé une nouvelle détection d'enveloppe permettant d'améliorer le rendement à faible puissance. Cette nouvelle détection d'enveloppe permet à l'amplificateur de classe G un fonctionnement en « multi niveau » et d'être auto adaptatif au signal audio présent en entrée de l'amplificateur. Après avoir développé des méta-modèles pour optimiser les paramètres de la détection d'enveloppe, cette détection d'enveloppe a été implémentée au niveau transistor en technologie 0.25μm de ST Microelectronics. / Embedded systems such as mobile phones, tablets and GPS incorporate an increasing number of electronic functions that generate a decrease in battery life. The aim of this work is to propose new solutions for audio amplifiers for the headphone application because this application has a large impact on battery autonomy. To improve the efficiency of actual amplifiers, a behavioral model of this kind of amplifier has been developed and validated by practical measures. This model, fast, accurate and reconfigurable allows in few seconds to evaluate the efficiency, consumption and quality of sound reproduction in real conditions of operation. Through the use of this model coupled with an optimizing method based on two algorithms, several architectures of level detector were studied and compared allowing to define the best compromise. A new architecture is then proposed, simulated and optimized in a 0.25μm technology from ST Microelectronics to demonstrate the feasibility of the solution.

Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquence. / This thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation.

L’objectif de ce travail est de concevoir et de caractériser un front-end millimétriqueutilisant des lignes de propagation à ondes lentes S-CPW optimisées en technologies CMOS avancées.Ces lignes présentant des facteurs de qualité 2 à 3 fois supérieurs à ceux des lignes classiques de typemicroruban ou CPW.Dans le premier chapitre, l’impact de l’évolution des noeuds technologiques CMOS sur lesperformances des transistors MOS aux fréquences millimétriques et sur les lignes de propagation ainsiqu’un état de l’art concernant les performances des front-end sont présentés. Le deuxième chapitreconcerne la réalisation des lignes S-CPW dans différentes technologies CMOS et la validation d’unmodèle phénoménologique électrique équivalent. Le troisième chapitre est dédié à la conceptiond’amplificateurs de puissance à 60 GHz utilisant ces lignes S-CPW en technologies CMOS 45 et65 nm. Cette étude a permis de mettre en évidence l’apport des lignes à ondes lentes aux performancesdes amplificateurs de puissance fonctionnant dans la gamme des fréquences millimétriques. Uneméthode de conception basée sur les règles d’électro-migration et permettant une optimisation desperformances a été développée. Finalement, un amplificateur faible bruit et un commutateur d’antennetravaillant à 60 GHz et à base de lignes S-CPW ont été conçus en technologie CMOS 65 nm afin degénéraliser l’impact de ce type de lignes sur les performances des front-end millimétriques. / The objective of this work is to design and characterize a millimeter-wave front-end usingthe optimized slow-wave transmission lines S-CPW in advanced CMOS technologies. The qualityfactor of these transmission lines is twice to three times higher than that of the conventionaltransmission lines such as microstrip lines and coplanar waveguides.In the first chapter, the influence of CMOS scaling-down on the performance of transistors atmillimeter-wave frequencies and on the transmission lines was studied. In addition, a state of the artwith regard to the performance of the front-end was presented. The second chapter concerns about therealization of the S-CPW lines in different CMOS technologies and the validation of an electricalequivalent model. The third chapter is dedicated to the design of 60-GHz power amplifiers using theseS-CPW lines in CMOS 45 and 65 nm technologies. This study highlighted the performanceenhancement of power amplifiers operating at millimeter-wave frequencies by using the slow-wavetransmission lines. A design method based on the electro-migration rules was also developed. Finally,a low noise amplifier and an antenna switch operating at 60 GHz were designed in CMOS 65 nm inorder to generalize the impact of such transmission lines on the performance of the millimeter-wavefront-end.

This thesis describes the analysis, design and implementation of a high performance DSP-based servo drive for a limited-angle torque motor used in thermal imaging applications. A limited-angle torque motor is an electromagnetic actuator based on the Laws' relay principle, and in the present application the rotation required was from - 10° to + 10° in 16 ms, with a flyback period of 4 ms. To ensure good quality picture reproduction, an exceptionally high linearity of ±0.02 ° was necessary throughout the forward sweep. In addition, the drive voltage to the exciting winding of the motor should be less than the +35 V ceiling of the drive amplifier. A research survey shows that little literature was available, probably due to the commercial sensitivity of many of the applications for torque motors. A detailed mathematical model of the motor drive, including high-order linear dynamics and the significant nonlinear characteristics, was developed to provide an insight into the overall system behaviour. The proposed control scheme uses a multicompensator, multi-loop linear controller, to reshape substantially the motor response characteristic, with a non-linear adaptive gain-scheduled controller to compensate effectively for the nonlinear variations of the motor parameters. The scheme demonstrates that a demanding nonlinear control system may be conveniently analysed and synthesised using frequency-domain methods, and that the design techniques may be reliably applied to similar electro-mechanical systems required to track a repetitive waveform. A prototype drive system was designed, constructed and tested during the course of the research. The drive system comprises a DSP-based digital controller, a linear power amplifier and the feedback signal conditioning circuit necessary for the closed-loop control. A switch-mode amplifier was also built, evaluated and compared with the linear amplifier. It was shown that the overall performance of the linear amplifier was superior to that of the switch-mode amplifier for the present application. The control software was developed using the structured programming method, with the continuous controller converted to digital form using the bilinear transform. The 6- operator was used rather than the z-operator, since it is more advantageous for high speed sampling systems. The gain-scheduled control was implemented by developing a schedule table, which is controlled by the DSP program to update continuously the controller parameters in synchronism with the periodic scanning of the motor. The experimental results show excellent agreement with the simulated results, with linearity of ±0.05 ° achieved throughout the forward sweep. Although this did not quite meet the very demanding specifications due to the limitations of the experimental drive system, it clearly demonstrates the effectiveness of the proposed control scheme. The discrepancies between simulated and experimental results are analyzed and discussed, the control design method is reviewed, and detailed suggestions are presented for further work which may improve the drive performance.